Semiconductor devices and fabrication methods thereof

Abstract

A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   a first semiconductor chip disposed on the substrate having a first through via and a dummy through via; and   a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip comprises an internal circuit;   wherein the first through via is electrically connected to the internal circuit of the second semiconductor chip, wherein the dummy through via is electrically insulated from the internal circuit of second semiconductor chip.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising:
 a first mold layer disposed on the first semiconductor chip covering the second semiconductor chip; and   a second mold layer on the substrate covering the first mold layer.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the first mold layer is further extended to fill gap region between the substrate and the first semiconductor chip. 
     
     
         4 . The semiconductor package of  claim 2 , wherein the second mold layer is further provided to fill gap regions between the first and second semiconductor chips. 
     
     
         5 . The semiconductor package of  claim 1 , further comprising a package substrate, wherein the substrate is mounted on the package substrate. 
     
     
         6 . The semiconductor package of  claim 1 , further comprising a first connection element disposed between the substrate and the first semiconductor chip, wherein the first connection element is electrically connected to the first connection through via and electrically insulated from the dummy through via. 
     
     
         7 . The semiconductor package of  claim 6 , further comprising a first auxiliary element disposed between the substrate and the first semiconductor chip, wherein the first auxiliary element electrically is electrically connected to the dummy through via and electrically insulated from the first connection through via. 
     
     
         8 . The semiconductor package of  claim 1 , further comprising a second connection element disposed between the first and second semiconductor chips, wherein the second connection element electrically connects the first connection through via and the internal circuit of the second semiconductor chip, wherein the second connection element is electrically insulated from the dummy through via. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the second semiconductor chip has a second connection through via, wherein the second connection through via is electrically connected to the first connection through via and electrically insulated from the dummy through via. 
     
     
         10 . A semiconductor device comprising:
 a first semiconductor chip comprising an internal circuit, at least one connection element electrically connected to the internal circuit of the first semiconductor chip and at least one auxiliary element electrically insulated from the internal circuit of first semiconductor chip;   a plurality of first connection structures disposed on a first side of the first semiconductor chip;   a second semiconductor chip comprising an internal circuit and disposed on a second side of the first semiconductor chip; and   a plurality of second connection structures disposed between the first and second semiconductor chips and comprising at least one connection element electrically connected to the internal circuits of the first and second semiconductor chips,   wherein a number of the second connection structures is less than a number of the first connection structures,   wherein at least one of the first and second semiconductor chips is a Dynamic Random Access Memory (DRAM) chip, and the first connection element is disposed at a center portion thereof.   
     
     
         11 . A semiconductor device comprising:
 a first semiconductor chip comprising an internal circuit;   a plurality of first through vias disposed in the first semiconductor chip and electrically connected to the internal circuit of the first semiconductor chip;   a second semiconductor chip disposed on a second side of the first semiconductor chip; and   a plurality of second through vias disposed in the second semiconductor chip and electrically connected to the internal circuits of the first semiconductor chip and the second semiconductor chip,   wherein a number of the second through vias is different from a number of the first through vias.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the number of the second through via is less than the number of the first through via. 
     
     
         13 . The semiconductor device of  claim 11 , further comprising a first dummy through via penenstrating the first semiconductor chip and electrically insulated from the first and second through vias. 
     
     
         14 . The semiconductor package of  claim 13 , further comprising a plurality of connection elements disposed between the first and second semiconductor chips, wherein the connection elements are electrically connected to the first and second through vias and electrically insulated from the first dummy through via. 
     
     
         15 . The semiconductor package of  claim 11 , further comprising:
 a lower structure, wherein the first and second semiconductor chips are disposed on the lower structure;   a first mold layer disposed on the first semiconductor chip covering the second semiconductor chip; and   a second mold layer disposed on the lower structure covering the first mold layer.   
     
     
         16 . The semiconductor package of  claim 11 , further comprising a package substrate, wherein the lower structure is mounted on the package substrate.