High resolution current pulse analog measurement

Abstract

A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an ADC (analog-to-digital converter). The samples can be aggregated as a distribution in order to estimate the jitter of the input clock signal. Variability of the measurement system can be minimized through calibrating the device-under-test at specific points of PVT (process, voltage, and temperature) conditions. A confidence metric such as a standard of deviation can be derived from the associated samples. The measurement system can be included on a substrate that includes the oscillator that generates the input clock signal.

What is claimed is: 
     
         1 . A measurement device, comprising
 a controller that is arranged to select a duration of a measurement window during which a current pulse is to be generated on a substrate;   a current source that is arranged in the substrate and that is arranged to vary an amount of current in the current pulse in response to the selected duration of the measurement window; and   a timing capacitor that is arranged in the substrate, that is arranged to accumulate charge from the current pulse, and that is arranged to provide an indication of the accumulated charge.   
     
     
         2 . The device of  claim 1 , comprising an analog-to-digital converter (ADC) that is arranged to convert the indication of the accumulated charge into a resultant digital value. 
     
     
         3 . The device of  claim 2 , wherein the resultant digital value has at least 12 bits of resolution. 
     
     
         4 . The device of  claim 3 , wherein resultant digital value has a differential non-linearity that falls within a range of plus-or-minus two counts when the ADC has an operating voltage of around three volts. 
     
     
         5 . The device of  claim 2 , wherein the controller is arranged to provide an indication of the resultant digital value to a device that is arranged off of the substrate. 
     
     
         6 . The device of  claim 5 , wherein the controller is arranged to provide a plurality of the resultant digital values. 
     
     
         7 . The device of  claim 6 , wherein the controller is arranged to generate a quality metric from the plurality of the resultant digital values. 
     
     
         8 . The device of  claim 7 , wherein the quality metric provides an indication of the standard of deviation of the plurality of the resultant digital values. 
     
     
         9 . The device of  claim 1 , wherein the current source is turned on and off in response to a timing pulse that is to be measured. 
     
     
         10 . The device of  claim 9 , wherein the duration of the timing pulse is determined by an timing generator that is arranged in the substrate. 
     
     
         11 . The device of  claim 10 , wherein the duration of the measurement window is selected in response to the duration of the timing pulse. 
     
     
         12 . The device of  claim 1 , wherein the current source is arranged to vary the amount of current in the current pulse by selectively enabling one or more current switches that are coupled in parallel between a first power supply rail and an opposing power supply rail. 
     
     
         13 . The device of  claim 12 , further comprising an enable synchronizer that is arranged to toggle the enabled one or more current switches by synchronizing an external enable signal with the current pulse, wherein the external enable signal is generated from a clock domain that is different from a clock domain of the current pulse. 
     
     
         14 . A statistical measurement system, comprising
 a controller that is arranged to select a duration of a measurement window during which a timing signal is to be measured;   a current source that is arranged in the substrate and that is arranged to select a magnitude of a charging current in response to the selected duration of the measurement window;   an enable synchronizer that is arranged on the substrate and that is arranged to receive an external enable signal, to enable the current source when a first transition of the timing signal occurs after the received external enable signal, and to disable the current source when a second transition of the timing signal occurs that is different from the first transition; and   a timing capacitor that is arranged in the substrate, that is arranged to accumulate charge from the charging current, and that is arranged to provide an indication of the accumulated charge.   
     
     
         15 . The system of  claim 14 , wherein the second transition has a direction that is opposite the first transition. 
     
     
         16 . The system of  claim 14  comprising a buffer that is arranged to produce a buffered voltage that provides an indication of the accumulated charge. 
     
     
         17 . The system of  claim 16 , comprising an analog-to-digital converter that is arranged to provide a digital resultant value in response to the buffered voltage. 
     
     
         18 . A method, comprising
 selecting a duration of a measurement window during which a timing signal is to be measured;   selecting a magnitude of a charging current in response to the selected duration of the measurement window;   accumulating, in a capacitor of a substrate, charge from the charging current starting in response to a first transition of the timing signal and ending in response to a second transition of the timing signal; and   using an analog-to-digital converter (ADC) to provide a digital resultant value that provides an indication of the accumulated charge.   
     
     
         19 . The method of  claim 18 , wherein the charge is accumulated after an external enable trigger is received from a device that is not formed in the substrate. 
     
     
         20 . The method of  claim 19 , wherein resultant digital value has a differential non-linearity that falls within a range of plus-or-minus two counts when the ADC has an operating voltage of around three volts and wherein the resultant digital value is reported to the device that is not formed in the substrate.