Tapered fin field effect transistor

Abstract

A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

1 . A semiconductor structure comprising a semiconductor fin located on a substrate and laterally extending along a lengthwise direction with a substantially same vertical cross-sectional shape that includes a vertically tapered portion in which a width of sidewalls increases with a vertical distance between a horizontal interface between said substrate and said semiconductor fin. 
     
     
         2 . The semiconductor structure of  claim 1 , wherein said substantially same vertical cross-sectional shape has a mirror symmetry around a vertical axis passing through a geometrical center of said substantially same vertical cross-sectional shape. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein said substantially same vertical cross-sectional shape further includes a rectangular portion having a same width as a maximum width of said vertically tapered portion and adjoining an upper end of said vertically tapered portion. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein said substantially same vertical cross-sectional shape further includes another rectangular portion having a same width as a minimum width of said vertically tapered portion and adjoining a lower end of said vertically tapered portion. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein sidewalls of said vertically tapered portion are concave sidewalls. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein said vertically tapered portion has a cross-sectional shape of a trapezoid. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein a bottom side of said trapezoid coincides with said horizontal interface, and a top side of said trapezoid coincides with a topmost surface of said semiconductor fin. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein a vertical cross-sectional shape of said semiconductor fin along a vertical plane including said lengthwise direction includes a pair of tapered edges, wherein each of said tapered edges is congruent with a tapered edge of said substantially same vertical cross-sectional shape. 
     
     
         9 . The semiconductor structure of  claim 1 , further comprising at least another semiconductor fin located on said substrate, laterally spaced from said semiconductor fin, extending in directions that are parallel to said lengthwise direction, and having said substantially same vertical cross-sectional shape. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein said substrate includes an insulator layer, and said horizontal interface is an interface between said insulator layer and said semiconductor fin. 
     
     
         11 . The semiconductor structure of  claim 1 , further comprising:
 a gate dielectric in contact with a top surface and sidewall surfaces of said semiconductor fin; and   a gate electrode in contact with said gate dielectric.   
     
     
         12 . The semiconductor structure of  claim 11 , wherein said semiconductor fin includes a body region, a source region, and a drain region, and said semiconductor structure further comprises:
 a raised source region in contact with said source region and located outside said semiconductor fin; and   a raised drain region in contact with said drain region and located outside said semiconductor fin.   
     
     
         13 .- 25 . (canceled)