US2014304561A1PendingUtilityA1
Shared fuse wrapper architecture for memory repair
Est. expiryJun 11, 2029(~2.9 yrs left)· nominal 20-yr term from priority
G11C 29/4401G11C 29/785G11C 29/44G06F 11/1088G11C 29/802G11C 29/787G11C 2029/4402
41
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Cited by
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Claims
Abstract
A memory repair mechanism for the memories clustered across the multiple power domains and can be switched on and off independent of each other, thereby enabling low power operation. Enhancements in the shared Fuse Wrapper Architecture enable sharing of a plurality of parallel links connecting the memory blocks of each power domains to the Shared Fuse Wrapper architecture.
Claims
exact text as granted — not AI-modifiedWe claim:
1 . A method for memory repair across multiple power domains, said method comprising:
determining defective memory locations and corresponding repair data for each memory block in each power domain; encoding the address and the repair data of each defective memory location; storing the encoded address and repair data obtained by incremental encoding across power domains; decoding the encoded the address and the repair data during functional operation; and repairing the defective memory locations.
2 . The method as claimed in claim 1 , wherein the encoding of the defective memory addresses and repair data comprises:
transferring the memory repair status to a fuse wrapper to determine the number of defective memories, total repair data length and corresponding logical addresses of defective memory locations; and processing the repair status of each memory based on its header content as follows:
for status value 10, start encoding of a defective redundancy memory location; incrementing defective memory count; storing the logical address of defective memory location; and starting the repair data length count;
for a status value 11, incrementing the repair data length count;
for a status value 01, ending encoding of the defective redundancy memory location and storing the repair data length count;
ignoring a status value of 00, as it corresponds to data of non redundancy memory; and
transferring the actual repair data of the defective memory location to the fuse wrapper.
3 . The method as claimed in claim 1 , wherein the encoding of the defective memory addresses and repair data comprises:
transferring the memory repair status to fuse wrapper in order to determine the number of defective memories, their individual repair data lengths and corresponding offsets of the repair data of defective faulty memory locations; and processing the repair status of each memory based on its header content as follows: for status value of 01, start encoding of a redundancy memory location; incrementing the offset length till a next 0 is obtained which signifies the end of this redundancy memory location;
for status value of 11, incrementing the defective memory count and storing the repair data length till a next 0 is obtained;
ignoring a status value of 00, as it corresponds to data of non redundancy memory; and
transferring the actual repair data of the defective memory location to the fuse wrapper.
4 . The method as claimed in claim 1 , wherein storing the encoded addresses and repair data in a common set of fuse data registers.
5 . The method as claimed in claim 1 , wherein the decoding the encoded addresses and repair data comprises:
initializing by shifting the encoded data from Fuse Macro Cell to shared Fuse Wrapper and segregating the number of defective memories, their logical addresses and the repair data and storing these in shared Fuse Wrapper; repairing the memory; transferring 11 from fuse wrapper in order to configure the serial chain; wherein, if the location address matches with the defective memory address as stored in shared Fuse Wrapper, shift out that memory's repair data into the repair data register chain; and if the location address does not match, shift 0 into the repair data register chain.
6 . The method as claimed in claim 1 , wherein the decoding the encoded addresses and repair data comprises:
transferring the encoded addresses and repair data from Fuse Macro Cell to shared Fuse Wrapper and segregating the number of defective memories, offsets of the repair data, individual repair data lengths and the repair data and store these in Fuse Wrapper; loading the first offset value internally in the Fuse Wrapper; shifting 0's into the local repair data registers till the offset count becomes 0; loading the first repair data length internally in the Fuse Wrapper; shifting the repair data from the Fuse Wrapper into the repair data registers till the repair data length count becomes 0;
wherein, repeating the above mentioned steps for next offsets and repair data until all the repair data chains have been configured.
7 . The method as claimed in claim 1 , wherein the data to be fused in the fuse data registers is approximated by:
Fuse
Bits
=
1
+
∑
R
=
1
R
=
N
(
log
2
(
Mr
+
1
)
)
+
∑
R
=
1
R
=
N
(
Krd
Length
)
+
K
min
*
Log
2
(
Bf
)
+
Krd
(
max
)
where Mr is the number of redundancy memories in a power domain, Krd is the length of total repair data in a power domain, Kmin is the minimum number of memories to be always repaired, Bf is the no. of bypass flops corresponding to logical addresses and, which are one per redundancy memory & one per non-redundancy collar, and Krd (max) is the largest repair data length corresponding to Kmin memories across power domains.
8 . The method device as claimed in claim 1 , wherein the data to be fused in the fuse data registers is approximated by:
Fuse
Bits
=
(
header
)
+
∑
i
=
1
R
=
N
(
log
2
(
Mi
(
r
+
1
)
)
+
log
2
(
Offseti
)
*
K
min
+
Krd
-
reli
(
max
)
*
K
min
+
Krd
(
max
)
where i=1 to N denotes the total number of power domains, {log 2 (Offsea)*Kmin+Krd−reli(max)*Kmin}corresponds to the power domain that has the largest value of the sum, Offseti corresponds to the total repair data corresponding to all the repair memories in a power domain and Krd−reli corresponds to the maximum relative repair data length within a power domain.
9 . The method as claimed in claim 1 , wherein said memories are a SRAM or a DRAM or a ROM memory.
10 . The method as claimed in claim 1 further comprising providing a Shared Fuse Wrapper architecture for storing the repair data of the memory blocks in each power domain.
11 . The method as claimed in claim 1 further comprising providing at least one repair data register for storing memory repair data thereon, each of which is operatively coupled with a corresponding memory block and for transmitting the memory repair data.
12 . The method as claimed in claim 1 further comprising providing a plurality of parallel links for coupling the memory blocks of each power domains to a Shared Fuse Wrapper architecture.
13 . The method as claimed in claim 5 , wherein decoding the encoded addresses and repair data is performed in parallel for all serial link chains that are powered on.Join the waitlist — get patent alerts
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