Spacer process for on pitch contacts and related structures

Abstract

Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

We claim: 
     
         1 . An integrated circuit structure, comprising:
 a plurality of pillars extending on a first axis over a substrate;   first and second laterally spaced blocks formed of the same material as the pillars, the first and second blocks extending at least between a first and a last of the pillars on the first axis, wherein the pillars are disposed between and on the same level as the first and second blocks; and   spacers disposed on sides of the pillars and on sides of the first and the second blocks.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the pillars comprise photoresist. 
     
     
         3 . The integrated circuit structure of  claim 2 , wherein the first and second blocks comprise photoresist. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the spacers comprise silicon oxide. 
     
     
         5 . The integrated circuit structure of  claim 1 , further comprising at least one hard mask between the substrate and the pillars, the first block, and the second blocks. 
     
     
         6 . The integrated circuit structure of  claim 5 , wherein the at least one hard mask comprises:
 a first hard mask over the substrate; and   a second hard mask over the first hard mask layer.   
     
     
         7 . The integrated circuit structure of  claim 6 , wherein the first hard mask comprises amorphous carbon. 
     
     
         8 . The integrated circuit structure of  claim 7 , wherein the second hard mask comprises an anti-reflective coating. 
     
     
         9 . The integrated circuit structure of  claim 1 , wherein the first and second blocks comprise laterally extending fingers extending towards the pillars. 
     
     
         10 . The integrated circuit structure of  claim 9 , wherein the fingers are disposed between pairs of the pillars. 
     
     
         11 . The integrated circuit structure of  claim 1 , wherein the pillars form a row of pillars, wherein only one row of pillars is disposed between the first and the second blocks. 
     
     
         12 . The integrated circuit structure of  claim 11 , wherein a width of each of the pillars is about 60 nm or less. 
     
     
         13 . The integrated circuit structure of  claim 12 , wherein the width of each of the pillars is about 30 nm or less. 
     
     
         14 . The integrated circuit structure of  claim 12 , wherein spacers between pairs of neighboring pillars define an opening between each pair of neighboring pillars. 
     
     
         15 . The integrated circuit structure of  claim 14 , wherein a width of the opening is about 60 nm or less. 
     
     
         16 . The integrated circuit structure of  claim 15 , wherein the width of the opening is about 30 nm or less. 
     
     
         17 . The integrated circuit structure of  claim 1 , wherein a distance between the spacers at the sides of the pillars is about 50 nm or less. 
     
     
         18 . The integrated circuit structure of  claim 1 , further comprising a plurality of conductive interconnects below the spacers and the pillars, the pillars vertically aligned with at least some of the conductive interconnects. 
     
     
         19 . The integrated circuit structure of  claim 1 , wherein the integrated circuit structure is a memory device structure. 
     
     
         20 . The integrated circuit structure of  claim 19 , wherein the memory device structure is a flash memory structure.