Semiconductor storage device and semiconductor storage device control method

Abstract

When using a read circuit of a semiconductor memory device to read data in a memory cell through a bit line BLX, out of a bit line pair BL, BLX that have a complementary relationship to each other and are connected to the memory cell storing the data, control is performed by a discharge circuit disposed within the read circuit, based on the signal from the bit line BL and a signal indicating the memory cell, to prevent a rise in potential of an SOUT node of the read circuit, or to prevent a fall in potential of the SOUT node, according to the potentials of the bit line pair BL, BLX. The SOUT accordingly does not become a floating node, enabling reading malfunction due to leak current to be prevented and enabling increased reading speed.

What is claimed is: 
     
         1 . A semiconductor storage device, comprising:
 a memory cell that stores data;   a pair of bit lines connected to the memory cell;   a read circuit that reads data in the memory cell via a first bit line out of the pair of bit lines; and   a potential control circuit that, based on a signal from a second bit line out of the pair of bit lines and on a designation signal that designates the memory cell, effects control to prevent a rise in potential of an output terminal of the read circuit, or to prevent a fall in potential of the output terminal, in accordance with potentials of the first bit line and the second bit line.   
     
     
         2 . The semiconductor storage device of  claim 1 , wherein:
 when the first bit line is a first potential and the second bit line is a second potential that is higher than the first potential, the potential control circuit effects control so that current is output to the output terminal and the output terminal becomes the second potential; and   when the first bit line is the second potential and the second bit line is the first potential, the potential control circuit effects control so that current is output from the output terminal and the output terminal becomes the first potential.   
     
     
         3 . The semiconductor storage device of  claim 2 , wherein the potential control circuit is a discharge circuit including, connected in series, a first transistor that is switched ON or OFF based on a signal of the second bit line, and a second transistor that is switched ON or OFF based on a signal that designates the memory cell. 
     
     
         4 . The semiconductor storage device of  claim 3 , wherein:
 when the first transistor and the second transistor are ON, current is output from the output terminal to a ground terminal of the first transistor through the second transistor; and   when the first transistor is OFF, current is output from a power source to the output terminal through a third transistor that is connected to the output terminal.   
     
     
         5 . The semiconductor storage device of  claim 1 , wherein:
 when the first bit line is a first potential and the second bit line is a second potential that is higher than the first potential, the potential control circuit effects control so that current is output from the output terminal and the output terminal becomes the first potential; and   when the first bit line is the second potential and the second bit line is the first potential, the potential control circuit effects control so that current is output to the output terminal and the output terminal becomes the second potential.   
     
     
         6 . The semiconductor storage device of  claim 5 , wherein the potential control circuit is a charge circuit including, connected in series, a fourth transistor that is switched ON or OFF based on a signal of the second bit line, and a fifth transistor that is switched ON or OFF based on a signal that designates the memory cell. 
     
     
         7 . The semiconductor storage device of  claim 6 , wherein:
 when the fourth transistor and the fifth transistor are ON, current is output from a power source to the output terminal through the fourth transistor and the fifth transistor; and   when the fourth transistor is OFF, current is output from the output terminal through a sixth transistor that is connected to the output terminal, to a ground terminal of the sixth transistor.   
     
     
         8 . The semiconductor storage device of  claim 1 , wherein the potential of the first bit line and the potential of the second bit line have a complementary relationship to each other, and the second bit line is not employed to read data from the memory cell. 
     
     
         9 . The semiconductor storage device of  claim 1 , wherein:
 the semiconductor storage device comprises a plurality of the memory cells, the pairs of bit lines, the read circuits and the potential control circuits;   the respective output terminals of the plurality of read circuits are connected together;   a selection signal is input as the designation signal to a read target memory cell out of the plurality of memory cells, and the potential control circuits corresponding to the memory cells other than the read target are switched OFF.   
     
     
         10 . The semiconductor storage device of  claim 9 , wherein the plurality of memory cells includes a first plurality of memory cells and a second plurality of memory cells, and each of the plurality of the read circuits is commonly disposed for the first plurality of memory cells and the second plurality of memory cells. 
     
     
         11 . A semiconductor storage device control method for a semiconductor storage device that includes a memory cell that stores data and a pair of bit lines connected to the memory cell, the control method comprising:
 a read circuit of the semiconductor storage device reading data in the memory cell via a first bit line out of the pair of bit lines; and   a potential control circuit of the semiconductor storage device, based on a signal from a second bit line out of the pair of bit lines and on a designation signal that designates the memory cell, effecting control to prevent a rise in potential of an output terminal of the read circuit, or to prevent a fall in potential of the output terminal, in accordance with potentials of the first bit line and the second bit line.   
     
     
         12 . The semiconductor storage device control method of  claim 11 , wherein:
 when the first bit line is a first potential and the second bit line is a second potential that is higher than the first potential, the potential control circuit effects control so that current is output to the output terminal and the output terminal becomes the second potential; and   when the first bit line is the second potential and the second bit line is the first potential, the potential control circuit effects control so that current is output from the output terminal and the output terminal becomes the first potential.   
     
     
         13 . The semiconductor storage device control method of  claim 11 , wherein:
 when the first bit line is a first potential and the second bit line is a second potential that is higher than the first potential, the potential control circuit effects control so that current is output from the output terminal and the output terminal becomes the first potential; and   when the first bit line is the second potential and the second bit line is the first potential, the potential control circuit effects control so that current is output to the output terminal and the output terminal becomes the second potential.