Semiconductor packages having package-on-package structures

Abstract

A semiconductor package includes a lower package with a lower semiconductor chip on a lower package substrate, and an upper package with an upper semiconductor chip on an upper package substrate. The upper semiconductor chip has a plurality of chip pads and the upper package substrate has a plurality of substrate pads. The upper package is stacked on the lower package. The chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch. The upper package substrate has a plurality of connection lines that electrically connect the substrate pads to the chip pads.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a lower package including a lower semiconductor chip on a lower package substrate; and   an upper package, stacked on the lower package, including an upper semiconductor chip on an upper package substrate, the upper semiconductor chip having a plurality of chip pads and the upper package substrate having a plurality of substrate pads,   wherein the chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch, and   wherein the upper package substrate comprises a plurality of connection lines that electrically connect the substrate pads to the chip pads.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising a plurality of connection terminals that electrically connect the upper package to the lower package,
 wherein the connection terminals are provided between the upper package and the lower package.   
     
     
         3 . The semiconductor package of  claim 2 , wherein the lower package further comprises:
 a lower mold layer; and   a plurality of connection patterns on the lower mold layer, wherein the connection patterns are electrically connected to the connection lines.   
     
     
         4 . The semiconductor package of  claim 3 , wherein the lower mold layer comprises an opening exposing a portion of the lower package substrate, and
 wherein the connection patterns extend toward inside the opening to be electrically connected to the lower package substrate.   
     
     
         5 . The semiconductor package of  claim 4 , wherein the opening comprises at least one of a line-type trench and a plurality of holes arranged along lateral sides of the lower semiconductor chip. 
     
     
         6 . A semiconductor package, comprising:
 a lower package including a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, a lower mold layer encapsulating the lower semiconductor chip, and connection patterns on the lower mold layer that penetrate the lower mold layer to be electrically connected to the lower package substrate;   an upper package including an upper package substrate having substrate pads, and an upper semiconductor chip mounted on the upper package substrate, the upper package being stacked on the lower package; and   connection terminals interposed between the lower and upper packages, the connection terminals electrically connecting the lower and upper packages,   wherein the upper semiconductor chip includes chip pads having a pitch narrower than a pitch of the substrate pads,   wherein the upper package substrate includes connection lines that provide electrical paths between the substrate pads and the chip pads, and   wherein the connection lines allow the chip pads to access a wider pitch of the substrate pads to electrically connect the upper semiconductor chip to the lower package substrate.   
     
     
         7 . The semiconductor package of  claim 6 , wherein the lower package substrate comprises circuit patterns electrically connected to the connection patterns,
 wherein the lower mold layer comprises an opening that is spaced apart from a lateral side of the lower semiconductor chip and vertically penetrates the lower mold layer to expose the circuit patterns, and   wherein the connection patterns extend toward the lower package substrate to pass through the opening to be electrically connected to the circuit patterns.   
     
     
         8 . The semiconductor package of  claim 6 , wherein the upper semiconductor chip is disposed on the upper package substrate while a surface of the upper semiconductor chip faces the upper package substrate, and
 wherein the surface of the upper semiconductor chip contacts the upper package substrate.   
     
     
         9 . The semiconductor package of  claim 6 , wherein the lower package further includes internal terminals provided between the lower semiconductor chip and the lower package substrate,
 wherein the lower semiconductor chip is disposed on the lower package substrate to be electrically connected thereto through the internal terminals while a surface of the lower semiconductor chip faces the lower package substrate.   
     
     
         10 . The semiconductor package of  claim 6 , wherein the lower semiconductor chip comprises a logic chip and the upper semiconductor chip comprises a memory chip. 
     
     
         11 . A semiconductor package comprising:
 a package-on-package type package including lower and upper packages vertically stacked and electrically connected,   wherein the lower package comprises a lower semiconductor chip mounted on a lower package substrate and encapsulated by a lower mold layer,   wherein the upper package comprises an upper semiconductor chip having chip pads mounted on an upper package substrate without a gap between the upper semiconductor chip and the upper package substrate, and   wherein the upper package substrate includes connection lines electrically connected to the upper semiconductor chip, the connection lines configured to provide the chip pads with access to a wider pitch to electrically connect the upper semiconductor chip to the lower package substrate.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the upper package substrate comprises substrate pads having a pitch greater than a pitch of the chip pads. 
     
     
         13 . The semiconductor package of  claim 11 , wherein the package-on-package type package further comprises connection terminals provided between the lower and upper packages,
 wherein the lower package further comprises connection patterns disposed on the lower mold layer to be electrically connected to the connection terminals.   
     
     
         14 . The semiconductor package of  claim 13 , wherein the connection patterns penetrate through the lower mold layer to be electrically connected to the lower package substrate. 
     
     
         15 . The semiconductor package of  claim 14 , wherein the lower package further comprises an opening that penetrates through the lower mold layer and provides the connection patterns with paths toward the lower package substrate,
 wherein the opening comprises at least one of a line-type trench extending along lateral sides of the lower semiconductor chip and a plurality of holes arranged along the lateral sides of the lower semiconductor chip.   
     
     
         16 . The semiconductor package of  claim 11 , wherein the upper package excludes micro-bumps between the upper semiconductor chip and the upper package substrate. 
     
     
         17 . The semiconductor package of  claim 11 , wherein the lower semiconductor chip is embedded in the lower package substrate. 
     
     
         18 . The semiconductor package of  claim 12 , wherein the substrate pads are located at one of a center of, an edge of, a specific region of, and uniformly across a lower surface of the upper package substrate, and the chip pads are located at one of a center of, an edge of, and uniformly across an active surface of the upper semiconductor chip.