Output Buffer Circuit Capable of Enhancing Stability

Abstract

An output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal, wherein when the operational amplifier charges or discharges the second terminal to reach a predetermined level, the output control unit change a value of the variable impedance of the signal output path.

What is claimed is: 
     
         1 . An output buffer circuit of a source driver, comprising:
 an operational amplifier, having a first terminal as an output of the operational amplifier; and   an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal,   wherein when the operational amplifier charges or discharges the second terminal to reach a predetermined level, the output control unit changes a value of the variable impedance of the signal output path.   
     
     
         2 . The output buffer circuit of  claim 1 , wherein at a first time point when the operational amplifier starts to charge or discharge the second terminal, the output control unit generates a first value of the variable impedance of the signal output path, and at a second time point when the voltage level at the second terminal is detected to reach the predetermined level, the output control unit generates a second value of the variable impedance of the signal output path, wherein the second value is different from the first value. 
     
     
         3 . The output buffer circuit of  claim 2 , wherein after the second time point, the output control unit further gradually changes the value of the variable impedance of the signal output path. 
     
     
         4 . The output buffer circuit of  claim 2 , wherein between the first and second time point, the output control unit maintains the first value of the variable impedance of the signal output path. 
     
     
         5 . The output buffer circuit of  claim 2 , wherein the second value is greater than the first value. 
     
     
         6 . The output buffer circuit of  claim 1 , further comprising a control signal generation unit, coupled to the output control unit, for detecting the voltage level at the second terminal and generating one or more control signals for controlling the output control unit according to the detected voltage level at the second terminal. 
     
     
         7 . The output buffer circuit of  claim 1 , wherein the output control unit comprises one or more output switches to generate the variable impedance of the signal output path. 
     
     
         8 . The output buffer circuit of  claim 7 , wherein a number of the one or more output switches is greater than one, and all of the output switches are turned on when the operational amplifier starts to charge or discharge the second terminal, and part of the output switches are turned off when the voltage level at the second terminal is detected to reach the predetermined level. 
     
     
         9 . The output buffer circuit of  claim 8 , wherein part of the output switches are sequentially turned off after the voltage level at the second terminal is detected to reach the predetermined level. 
     
     
         10 . The output buffer circuit of  claim 7 , a number of the one or more output switches is greater than one, and when the operational amplifier starts to charge or discharge the second terminal, a first number of output switches among the output switches are turned on, and when the voltage level at the second terminal is detected to reach the predetermined level, a second number of output switches among the output switches are turned on, wherein the first number is greater than the second number. 
     
     
         11 . The output buffer circuit of  claim 7 , wherein the number of the one or more output switches is one, and the output switch is turned on when the operational amplifier starts to charge or discharge the second terminal, and the output switch is partly turned off when the voltage level at the second terminal is detected to reach the predetermined level. 
     
     
         12 . The output buffer circuit of  claim 11 , wherein the output switch is gradually turned more off after the voltage level at the second terminal is detected to reach the predetermined level. 
     
     
         13 . The output buffer circuit of  claim 7 , a number of the one or more output switches is one, and when the operational amplifier starts to charge or discharge the second terminal, the output switch has a first conductivity, and when the voltage level at the second terminal is detected to reach the predetermined level, the output switch has a second conductivity, wherein the first conductivity is greater than the second conductivity. 
     
     
         14 . An output buffer circuit of a source driver, comprising:
 an operational amplifier, having a first terminal as an output of the operational amplifier; and   one or more output switches, coupled between the output terminal of the operational amplifier and a second terminal for driving a load,   wherein when the operational amplifier starts to charge or discharge the second terminal, the one or more output switches has a first impedance, and   when the voltage level at the second terminal is detected to reach a predetermined level, the one or more output switches has a second impedance different from the first impedance.   
     
     
         15 . An output buffer circuit of a source driver, comprising:
 an operational amplifier, having a first terminal as an output of the operational amplifier; and   an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal,   wherein when the operational amplifier charges or discharges the second terminal for a predetermined time, the output control unit changes a value of the variable impedance of the signal output path.   
     
     
         16 . The output buffer circuit of  claim 15 , wherein at a first time point when the operational amplifier starts to charge or discharge the second terminal, the output control unit generates a first value of the variable impedance of the signal output path, and at a second time point when the operational amplifier charges or discharges the second terminal for the predetermined time, the output control unit generates a second value of the variable impedance of the signal output path, wherein the second value is different from the first value. 
     
     
         17 . The output buffer circuit of  claim 16 , wherein after the second time point, the output control unit further gradually changes the value of the variable impedance of the signal output path. 
     
     
         18 . The output buffer circuit of  claim 16 , wherein between the first and second time point, the output control unit maintains the first value of the variable impedance of the signal output path. 
     
     
         19 . The output buffer circuit of  claim 16 , wherein the second value is greater than the first value. 
     
     
         20 . The output buffer circuit of  claim 15 , further comprising a control signal generation unit, coupled to the output control unit, for detecting the voltage level at the second terminal and generating one or more control signals for controlling the output control unit according to the detected voltage level at the second terminal. 
     
     
         21 . The output buffer circuit of  claim 15 , wherein the output control unit comprises one or more output switches to generate the variable impedance of the signal output path. 
     
     
         22 . The output buffer circuit of  claim 21 , wherein a number of the one or more output switches is greater than one, and all of the output switches are turned on when the operational amplifier starts to charge or discharge the second terminal, and part of the output switches are turned off when the operational amplifier charges or discharges the second terminal for the predetermine time. 
     
     
         23 . The output buffer circuit of  claim 22 , wherein part of the output switches are sequentially turned off after the operational amplifier charges or discharges the second terminal for the predetermine time. 
     
     
         24 . The output buffer circuit of  claim 21 , a number of the one or more output switches is greater than one, and when the operational amplifier starts to charge or discharge the second terminal, a first number of output switches among the output switches are turned on, and when the operational amplifier charges or discharges the second terminal for the predetermine time, a second number of output switches among the output switches are turned on, wherein the first number is greater than the second number. 
     
     
         25 . The output buffer circuit of  claim 21 , wherein a number of the one or more output switches is one, and the output switch is turned on when the operational amplifier starts to charge or discharge the second terminal, and the output switch is partly turned off the operational amplifier charges or discharges the second terminal for the predetermine time. 
     
     
         26 . The output buffer circuit of  claim 25 , wherein the output switch is gradually turned more off after the voltage level at the second terminal is detected to reach the predetermined level. 
     
     
         27 . The output buffer circuit of  claim 21 , a number of the one or more output switches is one, and when the operational amplifier starts to charge or discharge the second terminal, the output switch has a first conductivity, and when the operational amplifier charges or discharges the second terminal for the predetermine time, the output switch has a second conductivity, wherein the first conductivity is greater than the second conductivity. 
     
     
         28 . An output buffer circuit of a source driver, comprising:
 an operational amplifier, having a first terminal as an output of the operational amplifier; and   one or more output switches, coupled between the output terminal of the operational amplifier and a second terminal for driving a load,   wherein when the operational amplifier starts to charge or discharge the second terminal, the one or more output switches has a first impedance, and   when the operational amplifier charges or discharges the second terminal for a predetermine time, the one or more output switches has a second impedance different from the first impedance.   
     
     
         29 . An output buffer circuit of a source driver, comprising:
 an operational amplifier, having a first terminal as an output of the operational amplifier; and   an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal,   wherein when the operational amplifier charges or discharges the second terminal, and after the second terminal reaches a stable state, and the output control circuit gradually changes the impedance of the signal output path.   
     
     
         30 . The output buffer circuit of  claim 29 , wherein the output control unit comprising:
 one or more output switches to generate the variable impedance of the output signal path.