US2014284756A1PendingUtilityA1

Semiconductor device

Assignee: TOSHIBA KKPriority: Jun 20, 2012Filed: May 7, 2014Published: Sep 25, 2014
Est. expiryJun 20, 2032(~5.9 yrs left)· nominal 20-yr term from priority
H10W 42/60H10W 42/20H10W 42/00H10D 62/111H10D 64/115H10D 62/393H10D 62/127H10D 64/112H10D 62/124H10D 30/665H10D 12/481H10D 30/668H01L 29/404H01L 29/0684H01L 23/552
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Claims

Abstract

A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 an element region;   a termination region, the termination region surrounding the element region;   a first semiconductor region of a first conductivity type that is placed in the element region and the termination region;   a plurality of pillars of a second conductivity type, the plurality of pillars forming an array of pillars, the array spanning at least portions of the element region and the termination region in a first direction, the pillars extending from an upper surface of the first semiconductor region into the first semiconductor region in a direction substantially perpendicular to a plane containing the first semiconductor region; and   a plurality of field plate electrodes that are arrayed in the first direction, the plurality of field plate electrodes above the plurality of pillars, the plurality of field plate electrodes separated from the plurality of pillars by an insulating film.   
     
     
         2 . The semiconductor device of  claim 1 , wherein each field plate electrode is located above a junction interface, the junction interfaces formed between each of the plurality of pillars and the first semiconductor region. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a single field plate electrode is located above more than one pillar. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the array of pillars spans the entire width of the termination region. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a cover electrode above one or more field plate electrodes in the termination region. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the cover electrode is electrically connected to the shield electrode. 
     
     
         7 . The semiconductor device of  claim 5 , further comprising a plurality of cover electrodes. 
     
     
         8 . The semiconductor device of  claim 5 , further comprising an interconnection layer located between the cover electrode and the plurality of field plate electrodes. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the interconnection layer is wider than the cover electrode. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the interconnection layer is also located between the shield electrode and the field plate electrodes. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the interconnection layer comprises at least one of tungsten or titanium. 
     
     
         12 . The semiconductor device of  claim 8 , wherein the interconnection layer is a monolayer film. 
     
     
         13 . A semiconductor device, comprising:
 an element region;   a termination region, the termination region surrounding the element region;   a first semiconductor region of a first conductivity type that is placed in the element region and the termination region;   a plurality of second semiconductor regions of a second conductivity type in the first semiconductor region, and being juxtaposed in a first direction that is substantially perpendicular to a plane containing the first semiconductor region;   a third semiconductor region of the second conductivity type that is above at least one of the plurality of second semiconductor regions in the element region;   a fourth semiconductor region of the first conductivity type that is above the third semiconductor region;   a first electrode that is in contact with the first semiconductor region, the third semiconductor region, and the fourth semiconductor region, via a first insulating film;   a second electrode that is electrically connected to the third semiconductor region and the fourth semiconductor region;   a third electrode that is electrically connected to the first semiconductor region; and   a plurality of fourth electrodes that are juxtaposed in the first direction, above the plurality of second semiconductor regions in the termination region and above the first semiconductor region in the termination region, via a second insulating film;.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein each of the plurality of fourth electrodes is above the junction interface of each of the plurality of second semiconductor regions and the first semiconductor region that is sandwiched by each of the plurality of second semiconductor regions. 
     
     
         15 . The semiconductor device according to  claim 13 , wherein at least one of the plurality of fourth electrodes is disposed above at least two of the plurality of second semiconductor regions. 
     
     
         16 . The semiconductor device according to  claim 13 , wherein the plurality of second semiconductor regions in the first semiconductor region extends to an outer edge of the termination region. 
     
     
         17 . The semiconductor device according to  claim 13 , further comprising:
 a fifth electrode that is electrically connected to the third electrode, and is placed above at least one of the plurality of fourth electrodes via a third insulating film; and   a plurality of sixth electrodes placed between the second electrode and the fifth electrode and above the plurality of fourth electrodes, via the third insulating film.   
     
     
         18 . The semiconductor device according to  claim 17 , further comprising:
 an interconnection layer that is placed between each of the plurality of sixth electrodes and the third insulating film,   wherein the width of the interconnection layer in the first direction is wider than the width of each of the plurality of sixth electrodes in the first direction.   
     
     
         19 . The semiconductor device according to  claim 17 , wherein each of the plurality of sixth electrodes is electrically connected to the second electrode or the fifth electrode. 
     
     
         20 . A semiconductor device, comprising:
 an element region;   a termination region, the termination region surrounding the element region;   a first semiconductor region of a first conductivity type that is in the element region and the termination region;   a second semiconductor region of the first conductivity type that is above the first semiconductor region;   a plurality of pillars of a second conductivity type, the plurality of pillars forming an array of pillars, the array spanning at least portions of the element region and the termination region in a first direction, the pillars extending from an upper surface of the second semiconductor region into the second semiconductor region in a direction substantially perpendicular to a plane containing the first semiconductor region;   a plurality of field plate electrodes that are arrayed in the first direction, the plurality of field plate electrodes disposed above the plurality of pillars, the plurality of field plate electrodes separated from the plurality of pillars by an insulating film;   a shield electrode that is electrically connected to a drain electrode, the shield electrode disposed above at least one of the plurality of field plate electrodes;   a plurality of cover electrodes, the cover electrodes disposed above the field plate electrodes in the termination region; and   an interconnection layer, the interconnection layer disposed below each cover electrode;   wherein   the array of pillars spans the entire width of the termination region,   the interconnection layer is wider than each cover electrode, and   the cover electrodes are electrically connected to a source electrode or the shield electrode.

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