Integrated Circuit On Corrugated Substrate

Abstract

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

1 . An integrated circuit (IC) comprising a plurality of transistors, wherein each of the plurality of transistors comprises:
 a source;   a drain;   a plurality of semiconductor ridges connecting the source and the drain to form a channel region; and   a gate over the plurality of semiconductor ridges,   wherein a centerline of a first one of the plurality of semiconductor ridges in each of the plurality of transistors is aligned with a first common centerline, and   wherein a depth of the source and the drain is less than a height of the plurality of semiconductor ridges.   
     
     
         2 . The IC of  claim 1 , further comprising a ridge insulator material between each of the plurality of semiconductor ridges, wherein the ridge insulator material is formed between sub-surface heavily doped regions of the plurality of parallel semiconductor ridges. 
     
     
         3 . The IC of  claim 1 , further comprising a ridge isolation material disposed between each of the plurality of semiconductor ridges. 
     
     
         4 . An integrated circuit (IC) comprising a plurality of transistors, wherein each of the plurality of transistors comprises:
 a source;   a drain;   a plurality of semiconductor ridges connecting the source and the drain to form a channel region; and   a gate over the plurality of semiconductor ridges,   wherein a centerline of a first one of the plurality of semiconductor ridges in each of the plurality of transistors is aligned with a first common centerline, and   wherein the plurality of semiconductor ridges are formed on an elevated base region, which extends a predetermined height above adjacent substrate surfaces, and the source and drain are formed adjacent the elevated base region.   
     
     
         5 . The IC of  claim 4 , further comprising a ridge insulator material between each of the plurality of semiconductor ridges, wherein the ridge insulator material is formed between sub-surface heavily doped regions of the plurality of parallel semiconductor ridges. 
     
     
         6 . The IC of  claim 4 , further comprising a ridge isolation material disposed between each of the plurality of semiconductor ridges. 
     
     
         7 . An integrated circuit (IC) comprising a plurality of transistors, wherein each of the plurality of transistors comprises:
 a source;   a drain;   a plurality of semiconductor ridges connecting the source and the drain to form a channel region; and   a gate over the plurality of semiconductor ridges,   wherein a centerline of a first one of the plurality of semiconductor ridges in each of the plurality of transistors is aligned with a first common centerline, and   wherein a depth of device isolation material below a base of the plurality of semiconductor ridges is at least equal to a height of the plurality of semiconductor ridges.   
     
     
         8 . An integrated circuit (IC) comprising a plurality of transistors, wherein each of the plurality of transistors comprises:
 a source;   a drain;   a plurality of semiconductor ridges connecting the source and the drain to form a channel region; and   a gate over the plurality of semiconductor ridges,   wherein a centerline of a first one of the plurality of semiconductor ridges in each of the plurality of transistors is aligned with a first common centerline, and   wherein a depth of device isolation material below a base of the plurality of semiconductor ridges is 5× greater than a height of the plurality of semiconductor ridges.   
     
     
         9 . An integrated circuit (IC) comprising:
 a first plurality of transistors, wherein each of the first plurality of transistors comprises:
 a source; 
 a drain; 
 a plurality of semiconductor ridges connecting the source and the drain to form a channel region; and 
 a gate over the plurality of semiconductor ridges, 
   wherein a centerline of a first one of the plurality of semiconductor ridges in each of the plurality of transistors is aligned with a first common centerline.   
     
     
         10 . The IC of  claim 9 , further comprising a ridge insulator material between each of the plurality of semiconductor ridges, wherein the ridge insulator material is formed between sub-surface heavily doped regions of the plurality of parallel semiconductor ridges. 
     
     
         11 . The IC of  claim 9 , further comprising a ridge isolation material disposed between each of the plurality of semiconductor ridges.