Address translation in a system using memory striping

Abstract

A system and associated methods are disclosed for translating virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a virtual memory address, comparing a portion of the received virtual memory address to each of a plurality of entries of a virtual memory address matching table, determining a matching row of the virtual memory address matching table for the portion of the received virtual memory address, shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with information from the matching row, and combining the shifted contiguous set of bits of the received virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table, and with low-order bits of the received virtual memory address, to produce a physical memory address.

I claim: 
     
         1 . A method of translating a virtual memory address to a physical memory address, comprising:
 receiving a virtual memory address;   comparing a portion of the received virtual memory address to each of a plurality of entries of a virtual memory address matching table;   determining a matching row of the virtual memory address matching table for the portion of the received virtual memory address;   shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with information regarding memory address translation associated with the determined matching row of the virtual memory address matching table; and   combining the shifted contiguous set of bits of the received virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table, and with low-order bits of the received virtual memory address, to produce a physical memory address.   
     
     
         2 . The method of  claim 1  wherein the combining comprises one of summing or performing an bitwise-OR. 
     
     
         3 . The method of  claim 1  wherein, prior to combining the shifted contiguous set of bits of the virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table and with low-order bits of the virtual memory address from outside of the contiguous set of bits of the virtual memory address to produce a physical memory address, the high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table and the low-order bits of the virtual memory address from outside of the contiguous set of bits of the virtual memory address are combined. 
     
     
         4 . The method of  claim 1  wherein the virtual address table is stored in a content addressable memory. 
     
     
         5 . The method of  claim 1  further comprising:
 providing an indication of the matching row, wherein the indication of the matching row causes the selection of the information regarding address translation associated with the matching row. 
 
     
     
         6 . The method of  claim 1  further comprising:
 reading data from, or writing data to, the memory location associated with the produced physical memory address. 
 
     
     
         7 . The method of  claim 1  wherein the low-order bits are outside of the contiguous set of bits of the virtual memory address. 
     
     
         8 . The method of  claim 1  wherein the produced physical memory address refers to a memory location associated with a different memory bank, different microprocessor, different processor board, or different machine than that associated with a process from which the virtual memory address was received. 
     
     
         9 . The method of  claim 1  further comprising:
 storing, for each virtual memory address pattern stored in the virtual memory address matching table: high-order bits of corresponding physical memory addresses for virtual memory addresses matching the virtual memory address pattern, a number of bits to shift for virtual memory addresses matching the virtual memory address pattern, a degree of shift for virtual memory addresses matching the virtual memory address pattern, and a shift-region starting index for virtual memory addresses matching the virtual memory address pattern. 
 
     
     
         10 . The method of  claim 1  wherein the values of bits in the original positions of the shifted contiguous set of bits are set to zero. 
     
     
         11 . The method of  claim 1  wherein a plurality of lowest order bits of the virtual memory address are not among the contiguous set of bits of the virtual memory address that are shifted. 
     
     
         12 . The method of  claim 1  wherein the information regarding memory address translation comprises a number of bits to shift, a degree of shift, and a starting bit position for the region to be shifted. 
     
     
         13 . The method of  claim 1  wherein the information regarding memory address translation comprises a degree of shift, a starting bit position for the region to be shifted, and an ending bit position for the region to be shifted. 
     
     
         14 . The method of  claim 1  wherein the determining a matching row comprises:
 determining, for each row of the virtual address table, whether the portion of the virtual memory address matches the row; 
 providing indications of a plurality of rows that matched to an arbiter; and 
 determining, at the arbiter, a first matching row of the plurality of matching rows. 
 
     
     
         15 . The method of  claim 1  wherein there is one virtual memory address matching table per processor core. 
     
     
         16 . The method of  claim 1  wherein the virtual memory address is received as part of a request for memory access. 
     
     
         17 . An apparatus for translating virtual memory addresses to physical memory addresses, comprising:
 a memory for storing a received virtual memory address;   a content addressable memory for comparing a portion of the received virtual memory address to each of a plurality of entries in a virtual memory address matching table and determining a matching row of the virtual memory address matching table for the portion of the received virtual memory address;   shifting logic for shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with information regarding memory address translation associated with the determined matching row of the virtual memory address matching table; and   combining logic for combining the shifted contiguous set of bits of the received virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table, and with low-order bits of the received virtual memory address, to produce a physical memory address.   
     
     
         18 . The apparatus of  claim 17  wherein the combining logic comprises at least two of multiplexing logic, summing logic, and bitwise-or logic. 
     
     
         19 . A method of translating a virtual memory address to a physical memory address, comprising:
 receiving a virtual memory address;   deriving information regarding memory address translation from high-order bits of the received virtual memory address;   shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with the information regarding memory address translation derived from the high-order bits of the received the virtual memory address; and   combining the shifted contiguous set of bits of the received virtual memory address with predetermined high-order physical memory address bits, and with low-order bits of the received virtual memory address, to produce a physical memory address.   
     
     
         20 . The method of  claim 19  wherein the information regarding memory address translation derived from the high-order bits of the received the virtual memory address comprises a number of bits to shift, a degree of shift, and a starting bit position for the region to be shifted.