Iii-v finfets on silicon substrate

Abstract

A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.

1 . A method for forming fin field effect transistors, comprising:
 forming one or more dielectric layers on a silicon substrate;   forming high aspect ratio trenches in the one or more dielectric layers down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1;   epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins;   etching the one or more dielectric layers to expose a portion of the fins;   epitaxially growing a barrier layer on the portion of the fins;   forming a gate stack over the fins in a transverse orientation relative to a longitudinal direction of the fins;   forming a spacer around the portion of the fins and the gate stack;   implanting dopants into the portion of the fins; and   growing source and drain regions over the fins using a non-silicon containing semiconductor material.   
     
     
         2 . The method as recited in  claim 1 , wherein the non-silicon containing semiconductor material includes at least one of a III-V material and a II-VI material. 
     
     
         3 . The method as recited in  claim 1 , wherein epitaxially growing a non-silicon containing semiconductor material includes:
 growing the non-silicon containing semiconductor material above a height of the trench; and   planarizing the non-silicon containing semiconductor material to form the fins.   
     
     
         4 . The method as recited in  claim 1 , wherein etching the one or more dielectric layers to expose a portion of the fins includes etching the one or more dielectric layers in a guard-ring area down to the substrate. 
     
     
         5 . The method as recited in  claim 4 , wherein epitaxially growing a non-silicon containing semiconductor material includes growing the non-silicon containing semiconductor material in the guard-ring area. 
     
     
         6 . The method as recited in  claim 1 , wherein the fins include a III-V semiconductor material and the barrier layer includes a III-V semiconductor material. 
     
     
         7 . The method as recited in  claim 1 , wherein growing source and drain regions over the fins includes forming the source and drain regions over the fins by epitaxial growth and in-situ doping. 
     
     
         8 . The method as recited in  claim 1 , further comprising depositing a metal over the source and drain regions and annealing to mix the metal and the non-silicon containing semiconductor material of the source and drain regions. 
     
     
         9 . A method for forming fin field effect transistors, comprising:
 forming one or more dielectric layers on a silicon substrate;   forming high aspect ratio trenches in the one or more dielectric layers down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1;   epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins;   etching the one or more dielectric layers to expose a portion of the fins;   epitaxially growing a barrier layer on the portion of the fins;   forming a gate stack over the fins in a transverse orientation relative to a longitudinal direction of the fins;   forming a spacer around the portion of the fins and the gate stack;   etching the fins below at least a portion of the spacers; and   growing source and drain regions over a remaining portion of the fins using a non-silicon containing semiconductor material.   
     
     
         10 . The method as recited in  claim 9 , wherein the non-silicon containing semiconductor material includes at least one of a III-V material and a II-VI material. 
     
     
         11 . The method as recited in  claim 9 , wherein epitaxially growing a non-silicon containing semiconductor material includes:
 growing the non-silicon containing semiconductor material above a height of the trench; and   planarizing the non-silicon containing semiconductor material to form the fins.   
     
     
         12 . The method as recited in  claim 9 , wherein etching the one or more dielectric layers to expose a portion of the fins includes etching the one or more dielectric layers in a guard-ring area down to the substrate. 
     
     
         13 . The method as recited in  claim 12 , wherein epitaxially growing a non-silicon containing semiconductor material includes growing the non-silicon containing semiconductor material in the guard-ring area. 
     
     
         14 . The method as recited in  claim 9 , wherein the fins include a III-V semiconductor material and the barrier layer includes a III-V semiconductor material. 
     
     
         15 . The method as recited in  claim 9 , wherein growing source and drain regions over the remaining portion of the fins includes forming the source and drain regions over the remaining portion of the fins by epitaxial growth and in-situ doping. 
     
     
         16 . The method as recited in  claim 9 , further comprising depositing a metal over the source and drain regions and annealing to mix the metal and the non-silicon containing semiconductor material of the source and drain regions. 
     
     
         17 .- 20 . (canceled)