Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material

Abstract

A semiconductor device includes a first transistor having first drain and source regions and a first channel region and a second transistor having second drain and source regions and a second channel region. A first silicon/carbon alloy material is embedded in the first drain and source regions, the first silicon/carbon alloy material inducing a first strain component along a first channel length direction of the first channel region. A second silicon/carbon alloy material is embedded in the second drain and source regions, the second silicon/carbon alloy material inducing a second strain component along a second channel length direction of the second channel region, wherein the second strain component is of an opposite type of the first strain component.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a first transistor comprising first drain and source regions and a first channel region;   a first silicon/carbon alloy material embedded in said first drain and source regions, said first silicon/carbon alloy material inducing a first strain component along a first channel length direction of said first channel region;   a second transistor comprising second drain and source regions and a second channel region; and   a second silicon/carbon alloy material embedded in said second drain and source regions, said second silicon/carbon alloy material inducing a second strain component along a second channel length direction of said second channel region, said second strain component being of an opposite type of said first strain component.   
     
     
         22 . The semiconductor device of  claim 21 , further comprising a semiconductor material layer positioned above a buried insulating layer, wherein said first and second transistors are positioned in and above said semiconductor material layer. 
     
     
         23 . The semiconductor device of  claim 21 , wherein said first transistor is an N-channel transistor and said second transistor is a P-channel transistor. 
     
     
         24 . The semiconductor device of  claim 23 , wherein said first strain component is a tensile strain and second strain component is a compressive strain. 
     
     
         25 . The semiconductor device of  claim 21 , further comprising a stressed dielectric material layer positioned above each of said first and second transistors. 
     
     
         26 . The semiconductor device of  claim 25 , wherein said stressed dielectric material layer positioned above said first transistor is a first stressed material layer having an internal tensile stress. 
     
     
         27 . The semiconductor device of  claim 26 , wherein said stressed dielectric material layer positioned above said second transistor is a second stressed material layer having an internal compressive stress. 
     
     
         28 . The semiconductor device of  claim 21 , wherein said first transistor comprises a first sidewall spacer structure formed adjacent to a first gate electrode structure and said second transistor comprises a second sidewall spacer structure formed adjacent to a second gate electrode structure, at least one of said first and second sidewall spacer structures comprising a dielectric material having an internal stress level. 
     
     
         29 . The semiconductor device of  claim 21 , wherein a gate electrode structure of at least one of said first and second transistors comprises a conductive metal gate electrode and a gate insulation layer comprising a high-k gate dielectric material. 
     
     
         30 . A semiconductor device, comprising:
 a first and second active regions positioned in a layer of semiconductor material;   a first transistor element positioned in and above said first active region, wherein source and drain regions of said first transistor element comprise a first silicon/carbon alloy material that induces a tensile strain in a channel region of said first transistor element; and   a second transistor element positioned in and above said second active region, wherein source and drain regions of said second transistor element comprise a second silicon/carbon alloy material that induces a compressive strain in a channel region of said second transistor element.   
     
     
         31 . The semiconductor device of  claim 30 , wherein said layer of semiconductor material is positioned above a buried insulating layer. 
     
     
         32 . The semiconductor device of  claim 31 , wherein said source and drain regions of at least one of said first and second transistor elements extend down to said buried insulating layer. 
     
     
         33 . The semiconductor device of  claim 30 , wherein said first transistor element is an N-channel transistor and said second transistor element is a P-channel transistor. 
     
     
         34 . The semiconductor device of  claim 30 , further comprising a first stressed material layer having a first type of internal stress positioned on said first transistor element. 
     
     
         35 . The semiconductor device of  claim 34 , wherein said first type of internal stress of said first stressed material layer is a tensile stress. 
     
     
         36 . The semiconductor device of  claim 34 , wherein said first stressed material layer is a silicon nitride material layer having an internal tensile stress of at least approximately 1 GPa. 
     
     
         37 . The semiconductor device of  claim 34 , further comprising a second stressed material layer having a second type of internal stress positioned on said second transistor element, wherein said second type of internal stress is opposite of said first type of internal stress. 
     
     
         38 . The semiconductor device of  claim 37 , wherein said second type of internal stress of said second stressed material layer is a compressive stress. 
     
     
         39 . The semiconductor device of  claim 37 , wherein said second stressed material layer is a silicon nitride material layer having an internal compressive stress of at least approximately 2 GPa.