Performance Enhancement of Forming-Free ReRAM Devices Using 3D Nanoparticles

Abstract

Resistive random access memory (ReRAM) cells can include an embedded metal nanoparticle switching layer and electrodes. The metal nanoparticles can be formed using a micelle solution. The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents.

What is claimed is: 
     
         1 . A resistive random access memory cell comprising:
 a first layer operable as a first electrode;   a second layer operable as a resistive switching layer, wherein the second layer is disposed above the first layer, wherein the second layer comprises one or more arrays of metal nanoparticles, wherein the arrays of metal nanoparticles are disposed inside the second layer;   a third layer operable as a second electrode, wherein the third layer is disposed above the second layer.   
     
     
         2 . A memory cell as in  claim 1 , wherein the array of metal nanoparticles is disposed at an interface of the switching layer and an electrode. 
     
     
         3 . A memory cell as in  claim 1 , wherein a spacing between the array of metal nanoparticles and an electrode is between 1 and 10 nm. 
     
     
         4 . A memory cell as in  claim 1 , wherein the second layer comprises two or more arrays of metal nanoparticles, wherein a spacing between the two arrays of metal nanoparticles is between 1 and 10 nm. 
     
     
         5 . A memory cell as in  claim 1 , wherein a spacing between metal particles in the array of metal nanoparticles is between 1 and 10 nm. 
     
     
         6 . A memory cell as in  claim 1 , wherein a size of the metal particles is between 1 and 5 nm. 
     
     
         7 . A memory cell as in  claim 1 , wherein the second layer comprises two or more arrays of metal nanoparticles, wherein the two or more arrays of metal nanoparticles are aligned between the two electrodes. 
     
     
         8 . A memory cell as in  claim 1 , wherein the second layer comprises two or more arrays of metal nanoparticles, wherein the two or more arrays of metal nanoparticles are staggered between the two electrodes. 
     
     
         9 . A method of forming a resistive random access memory cell, the method comprising:
 providing a substrate comprising a first layer, wherein the first layer is operable as a first electrode;   depositing a second layer over the first layer, wherein the second layer comprises a first material which is operable as a resistive switching layer;   depositing an array of metal nanoparticles on the second layer;   depositing a third layer on the array of metal nanoparticles, wherein the third layer comprises the first material;   depositing a fourth layer over the third layer, wherein the fourth layer is operable as a second electrode.   
     
     
         10 . A method as in  claim 9 , further comprising
 depositing a second array of metal nanoparticles on the first layer before forming the second layer.   
     
     
         11 . A method as in  claim 9 , further comprising
 repeating the steps of depositing an array of metal nanoparticles and depositing the third layer.   
     
     
         12 . A method as in  claim 9 , further comprising
 depositing a third array of metal nanoparticles before forming the fourth layer.   
     
     
         13 . A method as in  claim 9 , further comprising
 annealing the first, second, and third layers at a temperature between 400 and 750 C.   
     
     
         14 . A method as in  claim 9 , wherein depositing the second layer comprises using atomic layer deposition (ALD). 
     
     
         15 . A method as in  claim 9 , wherein depositing the array of metal nanoparticles comprises coating with a micelle solution, wherein the micelle solution comprises micelles, wherein micelles comprises metal nanoparticles. 
     
     
         16 . A method of improving a performance of a resistive random access memory cell, wherein the resistive memory cell comprises a switching layer disposed between two electrodes, the method comprising:
 forming an array of metal nanoparticles in the switching layer;   controlling a vertical spacing of the metal nanoparticles, wherein the vertical spacing comprises a distance along a direction perpendicular to a surface of the electrodes;   controlling a lateral spacing of the metal nanoparticles, wherein the lateral spacing comprises a distance along a direction parallel to a surface of the electrodes.   
     
     
         17 . A method as in  claim 18 , wherein controlling a vertical spacing of the metal nanoparticles comprises controlling a deposition thickness of the switching layer. 
     
     
         18 . A method as in  claim 18 , wherein controlling a lateral spacing of the metal nanoparticles comprises controlling a separation of the metal nanoparticles in a micelle solution, wherein the micelle solution is used to form the array of metal nanoparticles in the switching layer. 
     
     
         19 . A memory cell as in  claim 18 , wherein the deposition thickness of the switching layer is less than 10 nm. 
     
     
         20 . A memory cell as in  claim 18 , wherein the separation of the metal nanoparticles in a micelle solution is less than 10 nm.