US2014246773A1PendingUtilityA1

Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate

Assignee: DIALOG SEMICONDUCTOR GMBHPriority: Mar 4, 2013Filed: Mar 8, 2013Published: Sep 4, 2014
Est. expiryMar 4, 2033(~6.6 yrs left)· nominal 20-yr term from priority
Inventors:Ian Kent
H10W 90/734H10W 90/728H10W 90/724H10W 90/722H10W 90/28H10W 74/142H10W 74/00H10W 72/07252H10W 72/252H10W 72/227H10W 70/682H10W 90/701H10W 74/117H10W 74/47H10W 74/016H10W 74/15H10W 74/012H10W 72/072H10W 70/69H10W 70/68H10W 70/66H10W 90/00H01L 24/81H01L 24/17
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Claims

Abstract

An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of fabricating a mother and daughter integrated circuit device comprising:
 providing a mother die having an active surface;   providing a daughter die having an active surface wherein said daughter die is smaller than said mother die in all dimensions;   directly connecting said active surface of said daughter die to said active surface of said mother die resulting in a pyramid die stack;   providing a substrate having a cavity drilled therein wherein said cavity corresponds to a size and position of said daughter die in relation to said mother die; and   attaching said pyramid die stack to said substrate using a flip chip method wherein said daughter die fits into said cavity.   
     
     
         2 . The method according to  claim 1  wherein said mother die is a power management circuit chip. 
     
     
         3 . The method according to  claim 1  wherein said daughter die is an integrated passive device containing at least one passive device. 
     
     
         4 . The method according to  claim 3  wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter. 
     
     
         5 . The method according to  claim 1  wherein said directly connecting said active surface of said daughter die to said active surface of said mother die comprises micro bumps. 
     
     
         6 . The method according to  claim 1  wherein said cavity is drilled by a mechanical drilling process or a laser drilling process. 
     
     
         7 . The method according to  claim 1  wherein said substrate is a ball grid array or a land grid array substrate. 
     
     
         8 . The method according to  claim 1  wherein said attaching said pyramid die stack to said substrate comprises copper pillar interconnects. 
     
     
         9 . A method of fabricating an integrated passive device comprising:
 providing a first die containing at least one power management device;   providing a second die containing at least one passive device wherein said second die is smaller than said first die;   directly connecting an active surface of said second die to an active surface of said first die resulting in a die stack;   providing a substrate having a cavity drilled therein wherein said cavity corresponds to a size and position of said second die in relation to said first die; and   attaching said die stack to said substrate using a flip chip method wherein said second die fits into said cavity.   
     
     
         10 . The method according to  claim 9  wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter. 
     
     
         11 . The method according to  claim 9  wherein said directly connecting said active surface of said second die to said active surface of said first die comprises micro bumps. 
     
     
         12 . The method according to  claim 9  wherein said cavity is drilled by a mechanical drilling process or by a laser drilling process. 
     
     
         13 . The method according to  claim 9  wherein said substrate is a ball grid array or a land grid array substrate. 
     
     
         14 . The method according to  claim 9  wherein said attaching said die stack to said substrate comprises copper pillar interconnects. 
     
     
         15 . A mother and daughter integrated circuit comprising:
 a mother die having an active surface;   a daughter die having an active surface wherein said daughter die is smaller than said mother die and wherein an active surface of said daughter die is directly connected to an active surface of said mother die resulting in a pyramid die stack; and   a substrate having a cavity drilled therein wherein said pyramid die stack is flip-chip attached to said substrate wherein said daughter die fits into said cavity.   
     
     
         16 . The device according to  claim 15  wherein said mother die is a power management circuit chip. 
     
     
         17 . The device according to  claim 15  wherein said daughter die is an integrated passive device containing at least one passive device. 
     
     
         18 . The device according to  claim 17  wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter. 
     
     
         19 . The device according to  claim 15  wherein said substrate is laminate substrate. 
     
     
         20 . The device according to  claim 15  wherein said substrate is a ball grid array or a land grid array substrate.

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