Methods for manufacturing semiconductor devices using etch stop dielectric layers and related devices

Abstract

A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate;   an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer includes first and second trenches spaced apart on the substrate;   a first gate dielectric layer on sidewall and bottom surfaces of the first trench;   a second gate dielectric layer on sidewall and bottom surfaces of the second trench;   an etch stop dielectric layer on the second gate dielectric layer in the second trench wherein the etch stop dielectric layer and the second gate dielectric layer comprise different materials;   a first metal gate layer on the first gate dielectric layer in the first trench; and   a second metal gate layer on the etch stop dielectric layer in the second trench, wherein the first and second metal gate layers have different work functions.   
     
     
         2 . The semiconductor device of  claim 1  further comprising:
 a first metal capping layer between the first gate dielectric layer and the first metal gate layer; and 
 a second metal capping layer between the second gate dielectric layer and the etch stop dielectric layer. 
 
     
     
         3 . The semiconductor device of  claim 1  wherein the etch stop dielectric layer comprises a second etch stop dielectric layer, the semiconductor device further comprising:
 a first etch stop dielectric layer on the first gate dielectric layer in the first trench wherein the first etch stop dielectric layer is between the first gate dielectric layer and the first metal gate layer. 
 
     
     
         4 . The semiconductor device of  claim 1  further comprising:
 first and second source/drain regions having a first conductivity type on opposite sides of the first trench; 
 a first channel region having a second conductivity type in the substrate between the first and second source/drain regions, wherein the first and second conductivity types are different; 
 third and fourth source/drain regions having the second conductivity type in the substrate on opposite sides of the second trench; and 
 a second channel region having the first conductivity type in the substrate between the third and fourth source/drain regions. 
 
     
     
         5 . The semiconductor device of  claim 1  wherein each of the first and second gate dielectric layers comprises a high-k dielectric material, and wherein the etch stop dielectric layer comprises at least one selected from the group consisting of metal oxide, metal oxynitride, metal silicon oxide, and/or metal silicon oxynitride. 
     
     
         6 . The semiconductor device of  claim 1  further comprising:
 a third metal gate layer on the etch stop dielectric layer so that the third metal gate layer is between the etch stop dielectric layer and the second metal gate layer wherein the second and third metal gate layers comprise different materials.