Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same

Abstract

In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.

1 . A memory cell comprising:
 a steering element; and   a memory element comprising:
 a first conductive material layer; 
 a first dielectric material layer disposed above the first conductive material layer; 
 a second conductive material layer disposed above the first dielectric material layer; 
 a second dielectric material layer disposed above the second conductive material layer; and 
 a third conductive material layer disposed above the second dielectric material layer, 
 wherein one or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. 
   
     
     
         2 . The memory cell of  claim 1 , wherein the first conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon. 
     
     
         3 . The memory cell of  claim 1 , wherein the first conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys. 
     
     
         4 . The memory cell of  claim 1 , wherein the second conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon. 
     
     
         5 . The memory cell of  claim 1 , wherein the second conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys. 
     
     
         6 . The memory cell of  claim 1 , wherein the first dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y  Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO. 
     
     
         7 . The memory cell of  claim 1 , wherein the second dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y  Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO. 
     
     
         8 . The memory cell of  claim 1 , wherein the steering element comprises a diode. 
     
     
         9 . The memory cell of  claim 1 , wherein the steering element comprises a vertically oriented diode. 
     
     
         10 . The memory cell of  claim 1 , wherein the steering element comprises a p-n, p-i-n, n-p-n or p-n-p punch-through diode, a carbon diode. 
     
     
         11 . The memory cell of  claim 1 , wherein the steering element comprises a thin film transistor. 
     
     
         12 . The memory cell of  claim 1 , wherein the memory element is disposed above or below the steering element. 
     
     
         13 . A method of programming a memory cell comprising a memory element comprising a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer, wherein one or both of the first conductive material layer and the second conductive material layer comprises a stack of a metal material layer and a highly doped semiconductor material layer, wherein the memory cell has a first memory state upon fabrication corresponding to a first read current, wherein the method comprises:
 applying a first programming pulse to the memory cell with a first current limit, wherein the first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.   
     
     
         14 . The method of  claim 13 , further comprising applying a second programming pulse to the memory cell with a second current limit higher than the first current limit, wherein the second programming pulse programs the memory cell to a third memory state that corresponds to a third read current greater than the second read current. 
     
     
         15 . The method of  claim 14 , further comprising applying a third programming pulse to the memory cell without a current limit, wherein the third programming pulse programs the memory cell to a fourth memory state that corresponds to a fourth read current greater than the third read current. 
     
     
         16 . The method of  claim 13 , wherein the first conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon. 
     
     
         17 . The method of  claim 13 , wherein the first conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys. 
     
     
         18 . The method of  claim 13 , wherein the second conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon. 
     
     
         19 . The method of  claim 13 , wherein the second conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys. 
     
     
         20 . The method of  claim 13 , wherein the first dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y  Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO. 
     
     
         21 . The method of  claim 13 , wherein the second dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y  Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO. 
     
     
         22 . A method of programming a memory cell comprising a memory element comprising a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer, wherein one or both of the first conductive material layer and the second conductive material layer comprises a stack of a metal material layer and a highly doped semiconductor material layer, wherein the method comprises:
 applying voltage pulses to the memory cell to reversibly switch the memory element between a low-resistivity state and a high-resistivity state.   
     
     
         23 . The method of  claim 22 , wherein the first conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon. 
     
     
         24 . The method of  claim 22 , wherein the first conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys. 
     
     
         25 . The method of  claim 22 , wherein the second conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon. 
     
     
         26 . The method of  claim 22 , wherein the second conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys. 
     
     
         27 . The method of  claim 22 , wherein the first dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y  Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO. 
     
     
         28 . The method of  claim 22 , wherein the second dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y  Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO. 
     
     
         29 . A monolithic three-dimensional memory array comprising:
 a first memory level monolithically formed above a substrate, the first memory level comprising a plurality of memory cells, wherein each memory cell comprises:
 a steering element; and 
 a memory element comprising:
 a first conductive material layer; 
 a first dielectric material layer disposed above the first conductive material layer; 
 a second conductive material layer disposed above the first dielectric material layer; 
 a second dielectric material layer disposed above the second conductive material layer; and 
 a third conductive material layer disposed above the second dielectric material layer, 
 wherein one or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer; and 
 
   a second memory level monolithically formed above the first memory level.   
     
     
         30 . The monolithic three-dimensional memory array of  claim 29 , wherein each steering element comprises a diode. 
     
     
         31 . The monolithic three-dimensional memory array of  claim 29 , wherein each steering element comprises a vertically oriented diode. 
     
     
         32 . The monolithic three-dimensional memory array of  claim 29 , wherein each steering element comprises a p-n, p-i-n, n-p-n or p-n-p punch-through diode or a carbon diode. 
     
     
         33 . The monolithic three-dimensional memory array of  claim 29 , wherein each steering element comprises a thin film transistor. 
     
     
         34 . The monolithic three-dimensional memory array of  claim 29 , wherein the memory elements are disposed above or below the steering element. 
     
     
         35 . The monolithic three-dimensional memory array of  claim 29 , wherein the first conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon. 
     
     
         36 . The monolithic three-dimensional memory array of  claim 29 , wherein the first conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys. 
     
     
         37 . The monolithic three-dimensional memory array of  claim 29 , wherein the second conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon. 
     
     
         38 . The monolithic three-dimensional memory array of  claim 29 , wherein the second conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys. 
     
     
         39 . The monolithic three-dimensional memory array of  claim 29 , wherein the first dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y  Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO. 
     
     
         40 . The monolithic three-dimensional memory array of  claim 29 , wherein the second dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y  Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO.