Semiconductor chip and semiconductor device

Abstract

Provided is a semiconductor chip that is flip-chip mounted where an inner chip pad array and an outer chip pad array, which are arranged on an inner side and an outer side of IO cells in a staggered manner, are arranged to be spaced away from each other by a predetermined gap or greater. The predetermined gap represents a gap where one via can be arranged between an inner substrate pad array and an outer substrate pad array on a substrate which faces and is connected to the inner chip pad array and the outer chip pad array. In addition, the predetermined gap represents a gap where a plated wire is interconnected and then a resist opening for etch-back can be formed. Even in a case where a space for forming an interconnection is not present between outer substrate pad arrays, interconnection characteristics of the substrate are improved.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor chip which includes a plurality of chip pads; and   a substrate on which the semiconductor chip is flip-chip mounted and which includes substrate pads that are connected to the chip pads, and a via,   wherein the semiconductor chip includes an input and output cell array that is constituted by a plurality of input and output cells including a first input and output cell, a second input and output cell, and a third input and output cell which are linearly arranged and are adjacent to each other,   the plurality of chip pads include a first pad that is electrically connected to the first input and output cell, a second pad that is electrically connected to the second input and output cell, and a third pad that is electrically connected to the third input and output cell,   the substrate includes a first substrate pad that faces and is connected to the first pad, a second substrate pad that faces and is connected to the second pad, and a third substrate pad that faces and is connected to the third pad,   a gap between the first substrate pad and the third substrate pad is narrower than the sum of a minimum width of an interconnection which is permitted from design constraints on the substrate and two times a space value that is required for the interconnection and each of the substrate pads,   in the semiconductor chip,   the first pad and the third pad are arranged adjacent to each other on a side further outward in comparison to the input and output cell array, and   the second pad is arranged on an inner side in comparison to the input and output cell array to be spaced away from each of the first pad and the third pad in such a manner that the second substrate pad is arranged to be spaced away from the first substrate pad and the third substrate pad by a distance that is equal to or greater than the sum of a diameter of the via provided to the substrate on which the semiconductor chip is flip-chip mounted and two times a minimum space value that is required for a gap between the via and each of the substrate pads in design constraints.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the semiconductor chip includes a first pad array in which a plurality of pads including the first pad and the third pad are adjacent to each other, and are linearly arranged in parallel with the input and output cell array on a side further outward in comparison to the input and output cell array, and   the plurality of pads which are arranged adjacent to each other in the first pad array are arranged with a minimum pitch that is required for a gap between pads of the semiconductor chip in design constraints.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein the semiconductor chip includes a second pad array in which a plurality of pads including the second pad are adjacent to each other, and are linearly arranged in parallel with the input and output cell array on a side further inward in comparison to the input and output cell array, and   the plurality of pads which are arranged adjacent to each other in the second pad array are arranged with a minimum pitch that is required for a gap between pads of the semiconductor chip in design constraints.   
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein the semiconductor chip further includes a fourth pad which is electrically connected to the second input and output cell and is arranged between the second pad and the input and output cell array on a side further inward in comparison to the input and output cell array, and   the substrate includes the first substrate pad that faces and is connected to the first pad, the second substrate pad that faces and is connected to the second pad, and the third substrate pad that faces and is connected to the third pad, and a substrate pad is not arranged at a position that faces the fourth pad.   
     
     
         5 . The semiconductor device according to  claim 3 ,
 wherein when the input and output cell array is set as a first input and output cell array, and a plurality of input and output cells, which are linearly arranged at one corner portion of the semiconductor chip in a direction perpendicular to the first input and output cell array, is set as a second input and output cell array, the semiconductor chip includes a third pad array that is linearly arranged in parallel with the second input and output cell array on a side further outward in comparison to the second input and output cell array, and   a plurality of pads that are arranged adjacent to each other in the third pad array are arranged with a minimum pitch that is required for a gap between pads of the semiconductor chip in design constraints.   
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein the substrate includes the first substrate pad that faces and is connected to the first pad, the second substrate pad that faces and is connected to the second pad, and the third substrate pad that faces and is connected to the third pad, and   the substrate includes an interconnection that connects the first substrate pad and the second substrate pad at the same interconnection layer as the first substrate pad and the second substrate pad, and a via that is connected to the interconnection and is arranged between the first substrate pad and the second substrate pad.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the substrate includes a BGA pad on a surface opposite to a surface provided with the substrate pads, and a BGA electrode that is connected to the BGA pad.   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein when the semiconductor chip is set as a first semiconductor chip, the semiconductor device further includes a second semiconductor chip that is stacked on the first semiconductor chip,   when the substrate pads are set as first substrate pad groups, the substrate further includes a second substrate pad group different from the first substrate pad groups on the same surface as the first substrate pad groups, and   the second semiconductor chip is connected to the second substrate pad group with a bonding wire.   
     
     
         9 . The semiconductor device according to  claim 7 , further comprising:
 a second semiconductor device that includes an protrusion electrode and is package-mounted,   wherein when the substrate pads are set as first substrate pad groups, the substrate further includes a second substrate pad group different from the first substrate pad groups on the same surface as the first substrate pad groups, and   the second semiconductor device is stacked by connecting the protrusion electrode and the second substrate pad group.   
     
     
         10 . A semiconductor chip comprising:
 an input and output cell array that is constituted by a plurality of input and output cells including a first input and output cell, a second input and output cell, and a third input and output cell which are linearly arranged and are adjacent to each other;   a first pad that is electrically connected to the first input and output cell;   a second pad that is electrically connected to the second input and output cell; and   a third pad that is electrically connected to the third input and output cell,   wherein a substrate on which the semiconductor chip is flip-chip mounted includes a first substrate pad that faces and is connected to the first pad, a second substrate pad that faces and is connected to the second pad, and a third substrate pad that faces and is connected to the third pad,   a gap between the first substrate pad and the third substrate pad is narrower than the sum of a minimum width of an interconnection which is permitted from design constraints on the substrate and two times a space value that is required for the interconnection and each of the substrate pads,   the first pad and the third pad are arranged adjacent to each other on a side further outward in comparison to the input and output cell array, and   the second pad is arranged on a side further inward in comparison to the input and output cell array to be spaced away from each of the first pad and the third pad by a distance that is equal to or greater than the sum of a diameter of a via provided to the substrate on which the semiconductor chip is flip-chip mounted and two times a minimum space value required for a gap between the via and each of the substrate pads on the substrate which is connected to each of the pads of the semiconductor chip in design constraints.   
     
     
         11 . The semiconductor chip according to  claim 10 ,
 wherein the semiconductor chip includes a first pad array in which a plurality of pads including the first pad and third pad are adjacent to each other, and are linearly arranged in parallel with the input and output cell array on a side further outward in comparison to the input and output cell array, and   the plurality of pads which are arranged adjacent to each other in the first pad array are arranged with a minimum pitch that is required for a gap between pads of the semiconductor chip in design constraints.   
     
     
         12 . The semiconductor chip according to  claim 11 ,
 wherein the semiconductor chip includes a second pad array in which a plurality of pads including the second pad are adjacent to each other, and are linearly arranged in parallel with the input and output cell array on a side further inward in comparison to the input and output cell array, and   the plurality of pads which are arranged adjacent to each other in the second pad array are arranged with a minimum pitch that is required for a gap between pads of the semiconductor chip in design constraints.   
     
     
         13 . The semiconductor chip according to  claim 10 , further comprising:
 a fourth pad which is electrically connected to the second input and output cell and is arranged between the second pad and the input and output cell array on a side further inward in comparison to the input and output cell array.   
     
     
         14 . The semiconductor chip according to  claim 12 ,
 wherein when the input and output cell array is set as a first input and output cell array, and a plurality of input and output cells, which are linearly arranged at one corner portion of the semiconductor chip in a direction perpendicular to the first input and output cell array, is set as a second input and output cell array,   the semiconductor chip includes a third pad array that is linearly arranged in parallel with the second input and output cell array on a side further outward in comparison to the second input and output cell array, and   a plurality of pads that are arranged adjacent to each other in the third pad array are arranged with a minimum pitch that is required for a gap between pads of the semiconductor chip in design constraints.