Transistor, resistance variable memory device including the same, and manufacturing method thereof

Abstract

A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first to work function.

What is claimed is: 
     
         1 . A transistor, comprising:
 an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region;   a first gate electrode formed to surround a periphery of the LDD region and having a first work function; and   a second gate electrode formed to be connected to the first gate electrode and to surround the channel region, and having a second work function that is higher than the first work function.   
     
     
         2 . The transistor of claim wherein the first gage electrode includes a transition metal layer including one selected from the group comprising titanium (Ti), tantalum (Ta), cobalt (Co), and platinum (Pt). 
     
     
         3 . The transistor of  claim 2 , wherein the second gate electrode includes a metal nitride layer. 
     
     
         4 . The transistor of  claim 2 , wherein the second gate electrode includes a transition metal silicide layer. 
     
     
         5 . The transistor of  claim 4 , wherein the second gate electrode is formed to have a thickness larger than a thickness of the first gate electrode. 
     
     
         6 . The transistor of  claim 1 , wherein the first gate electrode is formed on an outer circumference of the active pillar, and the second gate electrode is formed on an outer circumference of the first gate electrode. 
     
     
         7 . The transistor of  claim 6 , wherein the first gate electrode is formed to have a height shorter than that of the second gate electrode, and the second gate electrode is formed to overlap the active pillar without interposing of the first gate electrode. 
     
     
         8 . A resistance variable memory device, comprising:
 a vertical transistor including
 an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, 
 a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and 
 a second gate electrode formed to be connected to the first gate electrode and to surround the channel region, and having a second work function that is higher than the first work function; and 
   a resistive memory structure connected to the drain of the vertical transistor.   
     
     
         9 . The resistance variable memory device of  claim 8 , wherein the first gage electrode includes a transition metal layer including any one selected from the group comprising titanium (Ti), tantalum (Ta), cobalt (Co), and platinum (Pt). 
     
     
         10 . The resistance variable memory device of claim wherein the second gate electrode includes a metal nitride layer. 
     
     
         11 . The resistance variable memory device of  claim 8 , wherein the second gate electrode includes a transition metal silicide layer. 
     
     
         12 . The resistance variable memory device of  claim 8 , wherein the second gate electrode is formed to have a thickness larger than a thickness of the first gate electrode. 
     
     
         13 . The resistance variable memory device of  claim 8 , wherein the first gate electrode is formed on an outer circumference of the active pillar, and the second gate electrode is formed on an outer circumference of the first gate electrode. 
     
     
         14 . The resistance variable memory device of  claim 13 , wherein the first gate electrode is formed to have a height shorter than that of the second gate electrode, and the second gate electrode is formed to overlap the active pillar without interposing of the first gate electrode. 
     
     
         15 . The resistance variable memory device of  claim 8 , wherein the resistive memory structure includes:
 a lower electrode formed on the drain; and   a resistive memory layer formed on the lower electrode.   
     
     
         16 . The resistance variable memory device of  claim 15 , wherein the resistive memory layer includes one selected from the group comprising a PCMO layer including a material for a resistance random access memory (ReRAM), a chalcogenide layer including a material for a phase-change RAM (PCRAM), a magnetic layer including a material for a magentoresistive RAM (MRAM), a magnetization reversal device layer including a material for a spin-transfer torque magnetoresistive RAM (STTMRAM), and a polymer layer including a material for a polymer RAM (PoRAM). 
     
     
         17 . A method of manufacturing a resistance variable memory device, comprising:
 forming a source region in a semiconductor substrate;   forming a semiconductor layer on the source region;   patterning the semiconductor layer to form an active pillar;   forming a first gate electrode to surround the active pillar;   surrounding an upper region of the first gate electrode with an insulating layer while exposing a lower region of the first gate electrode; and   forming a second gate electrode by increasing a work function of the exposed first gate electrode.   
     
     
         18 . The method of  claim 17 , wherein the forming of the second gate electrode includes implanting nitrogen ions into the exposed lower region of the first gate electrode. 
     
     
         19 . The method of  claim 17 , wherein the forming of the second gate electrode includes:
 forming a silicon layer on the exposed lower region of the first gate electrode; and   forming a silicide layer by reacting the first gate electrode and the silicon layer.   
     
     
         20 . The method of  claim 17 , further comprising
 forming a lower electrode on the active pillar; and   forming a resistive memory layer on the lower electrode.   
     
     
         21 . A transistor, comprising:
 an active pillar including a channel region, a source formed at one an end of the channel region, a drain and a lightly doped drain (LDD) region formed at the other end of the channel region;   a first gate electrode formed to surround the LDD region and having a first work function; and   a second gate electrode formed to surround the channel region and having a second work function higher than the first work function.