Data processing system

Abstract

A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units.

I claim: 
     
         1 . Apparatus for processing data comprising:
 first processing circuitry configured to operate in a first power domain;   second processing circuitry configured to operate in a second power domain different from said first power domain;
 shared processing circuitry configured to operate in a shared power domain such that said first processing circuitry and said shared processing circuitry are configurable to operate together to form a first hybrid processing unit having access to an external memory and said second processing circuitry and said shared processing circuitry are configurable to operate together to form a second hybrid processing unit having access to said external memory, wherein said first hybrid processing unit and said second hybrid processing unit together comprise a uni-processing environment for executing a single instruction stream; 
 execution flow transfer circuitry for transferring execution of said single instruction stream between said first hybrid processing unit and said second hybrid processing unit at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point. 
   
     
     
         2 . Apparatus as claimed in  claim 1 , wherein said first processing circuitry and said second processing circuitry have different processing performance characteristics. 
     
     
         3 . Apparatus as claimed in  claim 2 , wherein said execution flow transfer circuitry comprises power control circuitry for independently controlling power to said first processing circuitry and said second processing circuitry such that each of said first processing circuitry and said second processing circuitry can be placed in a powered-up state in which it is ready to perform processing operations and a power-saving state in which it is awaiting activation. 
     
     
         4 . Apparatus as claimed in  claim 3 , wherein said power control circuitry is configured to independently control power to said shared circuitry. 
     
     
         5 . Apparatus as claimed in  claim 4 , wherein said power control circuitry is configured to control said shared circuitry to operate at a first level of power consumption when said first hybrid processing unit has control of execution of said single instruction stream and to operate at a second different level of power consumption when said second hybrid processing unit has control of execution of said single instruction stream. 
     
     
         6 . Apparatus as claimed in  claim 3 , wherein said power control circuitry is configured to switch one of said first processing circuitry and said second processing circuitry corresponding to said destination hybrid processing unit from said power-saving state to said powered-up state and to switch the other of said first processing circuitry and said second processing circuitry corresponding to said source hybrid processing unit from said powered-up state to said power-saving state as part of said execution transfer process. 
     
     
         7 . Apparatus as claimed in  claim 1 , comprising circuitry for stopping a clock signal to one of said first processing circuitry and said second processing circuitry that is not currently in control of execution of said single instruction stream. 
     
     
         8 . Apparatus as claimed in  claim 2 , wherein said first processing circuitry and said second processing circuitry are architecturally compatible and wherein said first processing circuitry differs micro-architecturally from said second processing circuitry. 
     
     
         9 . Apparatus as claimed in  claim 8 , wherein said architectural compatibility comprises compatibility of at least one of general purpose registers, control registers and instruction sets. 
     
     
         10 . Apparatus as claimed in  claim 8 , wherein said micro-architectural differences between said first processing circuitry and said second processing circuitry comprise at least one of: pipeline length, instruction issue width, cache configuration, branch prediction capability and translation lookaside buffer (TLB) configuration. 
     
     
         11 . Apparatus as claimed in  claim 2 , wherein one of said first processing circuitry and said second processing circuitry is higher performance processing circuitry relative to the other of said first processing circuitry and said second processing circuitry and wherein said other of said first processing circuitry and said second processing circuitry is higher efficiency processing circuitry relative to said one of said first processing circuitry and said second processing circuitry. 
     
     
         12 . Apparatus as claimed in  claim 11 , wherein said apparatus is fabricated on a single integrated circuit with said higher performance processing circuitry being substantially physically localized to a first area of said integrated circuit and said higher efficiency processing circuitry being substantially physically localized to a second area of said integrated circuit and wherein said second distinct area is different from said first distinct area. 
     
     
         13 . Apparatus as claimed in  claim 1 , wherein said shared processing circuitry comprises at least one of: cache circuitry, translation lookaside buffer circuitry, special purpose registers, bus interface circuitry, bus pins and trace circuitry. 
     
     
         14 . Apparatus as claimed in  claim 1 , wherein each of said first processing circuitry and said second processing circuitry comprises at least one of: a program counter, general purpose registers, branch prediction circuitry, decoding/sequencing circuitry, an execution datapath and load/store circuitry. 
     
     
         15 . Apparatus as claimed in  claim 1 , wherein said execution flow transfer circuitry is configured to initiate said transfer of execution of said single instruction stream from said source hybrid processing unit to said destination hybrid processing unit in response to a hardware trigger such that said transfer is functionally transparent to an operating system and software executing on said data processing apparatus. 
     
     
         16 . Apparatus as claimed in  claim 15 , wherein said hardware trigger is at least one of: a temperature sensor, a series of cache misses, initiation of a hardware page table walk, processing circuitry entering a polling state and processing circuitry entering a wait-for-interrupt state. 
     
     
         17 . Apparatus as claimed in  claim 1 , comprising performance-level varying circuitry configured to vary a processing performance level of at least one of said first hybrid processing unit and said second hybrid processing unit. 
     
     
         18 . Apparatus as claimed in  claim 17 , wherein said performance-level varying circuitry is configured to perform dynamic voltage and frequency scaling of processing performance of at least one of said first hybrid processing unit and said second hybrid processing unit by varying at least one of: a voltage of said first power domain; a voltage of said second power domain; a voltage of said shared power domain; a frequency of operation of said first processing circuitry; a frequency of operation of said second processing circuitry and a frequency of operation of said shared processing circuitry. 
     
     
         19 . Apparatus for processing data comprising:
 first means for processing configured to operate in a first power domain;   second means for processing configured to operate in a second power domain different from said first power domain;   means for shared processing configured to operate in a shared power domain such that said means for first processing and said means for shared processing are configurable to operate together to form a first means for hybrid processing having access to an external memory and said second means for processing and said means for shared processing are configurable to operate together to form a second means for hybrid processing having access to said external memory, wherein said first means for hybrid processing and said second means for hybrid processing together comprise a uni-processing environment for executing a single instruction stream;   means for execution flow transfer for transferring execution of said single instruction stream between said first means for hybrid processing and said second means for hybrid processing at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first means for hybrid processing and said second means for hybrid processing to a destination one of said first means for hybrid processing and said second means for hybrid processing, said processing-state restoration information being information enabling said destination means for hybrid processing to successfully resume execution of said single instruction stream from said transfer execution point.   
     
     
         20 . A data processing method comprising the steps of:
 operating first processing circuitry in a first power domain;   operating second processing circuitry in a second power domain different from said first power domain;   operating shared processing circuitry in a shared power domain and forming a first hybrid processing unit by operating said first processing circuitry and said shared processing circuitry together, said first hybrid processing unit having access to an external memory;   forming a second hybrid processing unit by operating and said second processing circuitry and said shared processing circuitry together, said second hybrid processing unit having access to said external memory;   providing a uni-processing environment for executing a single instruction stream, said uni-processing environment comprising said hybrid processing circuitry and said second hybrid processing circuitry together;   transferring execution of said single instruction stream between said first hybrid processing circuitry and said second hybrid processing circuitry at a transfer execution point using transfer execution circuitry, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point.