Method and system for enhanced performance in serial peripheral interface

Abstract

A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed.

What is claimed is: 
     
         1 . An integrated circuit device having a plurality of memory cells for storing data, comprising:
 at least one pin for transferring an operating command for the memory cells, a first address associated with the memory cells, and data associated with the first address; and   a circuit being able to control the device in an enhanced operation which allows the omission of the some operating command for an transfer of data associated with a second address.   
     
     
         2 . The device of  claim 1 , wherein the enhanced operation is activated/deactivated by an enhanced operation indicator which is received in an interval after transferring the first address while before transferring the associated data. 
     
     
         3 . The device of  claim 2 , wherein the enhanced operation indicator is also received in an interval after transferring the second address while before transferring the data associated with the second address. 
     
     
         4 . The device of  claim 2 , wherein the enhanced operation indicator comprises a first bit and a second bit for determining whether the enhanced operation is to be performed. 
     
     
         5 . The device of  claim 4 , wherein the enhanced operation indicator includes a number of first bits P4, P5, P6, and P7 received in a first enhance indicator clock cycle and a number of second bits P0, P1, P2, and P3 received in a second enhance indicator clock cycle, the activation of enhanced operation is determined by comparing each of the first bits received in the first enhance indicator clock cycle to each corresponding one of the second bits received in the second enhance indicator clock cycle. 
     
     
         6 . The device of  claim 1 , wherein the operating command is operated for one of read and write, and the first address is an address for page mode. 
     
     
         7 . The device of  claim 1 , further comprises a serial peripheral interface pin configuration and the data are transferred using a plurality of pins concurrently. 
     
     
         8 . An integrated circuit device having a plurality of memory cells for storing data, comprising:
 at least one pin, in a first operation, configured to transfer an operating command for the memory cells, a first address associated with the memory cells, and a first data associated with the first address; and   a circuit for setting the device into an enhanced operation related to the first operation to transfer a second address and a second data associated with a second address under an omission of the operating command associated to the second address based upon an indication in the first operation.   
     
     
         9 . The device of  claim 8 , wherein the enhanced operation is activated/deactivated by an enhanced operation indicator which is received in an interval after transferring the first address and before transferring the associated data. 
     
     
         10 . The device of  claim 9 , wherein the performance enhancement indicator comprises a first bit and a second bit for determining whether the enhanced operation is to be performed. 
     
     
         11 . The device of  claim 10 , wherein the first bit and the second bit constitutes a code for this enhancement operation.