Highly Efficient Design of Storage Array Utilizing Multiple Cache Lines for Use in First and Second Cache Spaces and Memory Subsystems

Abstract

A method of operating a cache memory includes the step of storing a set of data in a first space in a cache memory, a set of data associated with a set of tags. A subset of the set of data is stored in a second space in the cache memory, the subset of the set of data associated with a tag of a subset of the set of tags. The tag portion of an address is compared with the subset of data in the second space in the cache memory in that said subset of data is read when the tag portion of the address and the tag associated with the subset of data match. The tag portion of the address is compared with the set of tags associated with the set of data in the first space in cache memory and the set of data in the first space is read when the tag portion of the address matches one of the sets of tags associated with the set of data in the first space and the tag portion of the address and the tag associated with the subset of data in the second space do not match.

1 - 16 . (canceled) 
     
     
         17 . A method of operating a cache memory comprising the steps of:
 storing a set of data in a first space in the cache memory, the set of data associated with a set of tags, the set of data in the first space in the cache memory being comprised of a first plurality of cache lines, each cache line in the first plurality of cache lines being associated with a valid indicator indicative as to whether data associated with the cache line is valid;   storing a subset of the set of data in a second space in the cache memory and associated with a tag, the tag associated with the subset of data and being a subset of the set of tags, the set of data in the second space in the cache memory being comprised of a second plurality of cache lines, each cache line in the second plurality of cache lines being associated with a valid indicator indicative as to whether data associated with the cache line is valid;   wherein one of the second plurality of the cache lines is associated with the tag associated with the subset of data   comparing a tag portion of an address with the tag associated with the subset of data in the second space in the cache memory;   reading the subset of data in the second space when the tag portion of the address and the tag associated with the subset of data match;   comparing the tag portion of the address with the set of tags associated with the set of data in the first space in the cache memory; and   reading the set of data in the first space when the tag portion of the address matches one of the set of tags associated with the set of data in the first space and the tag portion of the address and the tag associated with the subset of data in the second space do not match;   writing data associated with a write address from a processor coupled to the cache memory to a memory location of the first space in the cache memory;   comparing the tag portion of the write address with the tag associated with the subset of the set of data stored in the second space in the cache memory; and   setting the valid indicator of the cache line associated with the tag to indicate that the data associated with the cache line is invalid when the tag portion of the write address matches the tag associated with the subset of the set of data.   
     
     
         18 . The method of  claim 17  wherein the associativity of the first space in the cache memory and the second space in the cache memory is dynamic. 
     
     
         19 . The method of  claim 17  wherein the cache memory is part of a multiprocessor system. 
     
     
         20 . The method of  claim 17  wherein the cache memory is implemented using DRAM. 
     
     
         21 . The method of  claim 17  wherein the cache memory is implemented using SRAM. 
     
     
         22 . The method of  claim 17  wherein the cache memory is implemented using multi-ported memory. 
     
     
         23 . The method of  claim 17  further comprising the steps of:
 prefetching data into the first space in the cache memory; and 
 responding to a read request from a processor coupled to the cache memory with data from the second space in the cache memory. 
 
     
     
         24 . A processing system comprising:
 a system memory;   a cache memory comprising first and second peer cache memory spaces;   a processor coupled to the cache memory;   a first table for storing tags associated with data stored in the first cache memory space;   a second table for storing tags associated with data stored in the second cache memory space;   processing circuitry operable to:
 access a plurality of blocks of data from said system memory in response to a plurality of addresses; 
 store said blocks of data accessed from said system memory within said first cache memory space, said blocks of data associated with a set of tags in said first table, said blocks further being associated with a set of valid indicators, each valid indicator indicating whether data associated with a particular block is valid; 
 store a selected block of said blocks of data accessed from said system memory within said second cache memory space, the selected block being associated with a valid indicator indicative of whether the data associated with the block is valid, and said block associated with a tag in said second table; 
 generate a read address including a tag field; 
 compare said tag field of said read address with said tag in said second table associated with said selected block and access said selected block from said second cache memory space when said tag field and said tag in said second table match; 
 compare said tag field of said read address with said set of tags in said first table when said tag field and said tag in said second table do not match and access a corresponding block in said first cache memory space when said tag field and a tag in said first table match; and 
   the processing circuitry being further operable to write data associated with a write address from the processor to a block in the first cache memory space, compare the tag portion of the write address with the tag in said second table, and set the valid indicator associated with the block associated with the tag in said second table when the tag portion of the write address matches the tag in said second table.   
     
     
         25 . The system of  claim 24  wherein the processing circuitry is further operable to change the associativity of the first space in the cache memory and the second space in the cache memory dynamically. 
     
     
         26 . The system of  claim 24  further comprising a first processor coupled to the cache memory and a second processor coupled to the cache memory. 
     
     
         27 . The system of  claim 24  wherein the cache memory is implemented using DRAM. 
     
     
         28 . The system of  claim 24  wherein the cache memory is implemented using SRAM. 
     
     
         29 . The system of  claim 24  wherein the cache memory is implemented using multi-ported memory. 
     
     
         30 . The system of  claim 24  further comprising:
 prefetching circuitry operable to prefetch data into the first space in the cache memory; and wherein the processing circuitry is further operable to respond to a read request with data from the second space in the cache memory. 
 
     
     
         31 . The system of  claim 24  further comprising:
 a processor coupled to the cache memory; and 
 wherein the processing circuitry is further operable to read data from the first space in the cache memory; and 
 at substantially the same time write data to the second space in the cache memory.