Efficient validation of coherency between processor cores and accelerators in computer systems

Abstract

A method of testing cache coherency in a computer system design allocates different portions of a single cache line for use by accelerators and processors. The different portions of the cache line can have different sizes, and the processors and accelerators can operate in the simulation at different frequencies. The verification system can control execution of the instructions to invoke different modes of the coherency mechanism such as direct memory access or cache intervention. The invention provides a further opportunity to test any accelerator having an original function and an inverse function by allocating cache lines to generate an original function output, allocating cache lines to generate an inverse function output based on the original function output, and verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input.

1 . A method of testing coherency in a system design having a shared resource, at least one processor which accesses the shared resource, and at least one accelerator which accesses the shared resource, comprising:
 selecting an entry of the shared resource for targeted testing during a simulation of operation of the system design, by executing first instructions in a computer system;   allocating a first portion of the selected entry for use by one or more first instructions from the processor, by executing second instructions in the computer system;   allocating a second portion of the selected entry for use by one or more second instructions from the accelerator, by executing third instructions in the computer system;   executing the first and second instructions using the allocated first and second portions of the selected entry subject to a coherency protocol adapted to maintain data consistency of the shared resource, by executing fourth instructions in the computer system; and   verifying correctness of data stored in the entry, by executing fifth instructions in the computer system.   
     
     
         2 . The method of  claim 1  wherein the shared resource is a cache memory and the entry is a cache line of the cache memory. 
     
     
         3 . The method of  claim 1  wherein the processor and the accelerator operate in the simulation at different frequencies. 
     
     
         4 . The method of  claim 1  wherein the first portion of the selected entry is randomly allocated for use by the one or more first instructions, and the second portion of the selected entry is randomly allocated for use by the one or more second instructions. 
     
     
         5 . The method of  claim 1  wherein multiple processors access the shared resource, and further comprising allocating a third portion of the selected entry for use by one or more third instructions from a second processor. 
     
     
         6 . The method of  claim 1  wherein multiple accelerators access the shared resource, and further comprising allocating a third portion of the selected entry for use by one or more third instructions from a second accelerator. 
     
     
         7 . The method of  claim 1  wherein the accelerator has an original function and an inverse function which is opposite to the original function, and further comprising:
 allocating a first set of entries of the shared resource for the accelerator to generate an original function output based on an original function input; 
 allocating a second set of entries of the shared resource for the accelerator to generate an inverse function output based on the original function output; and 
 verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input. 
 
     
     
         8 - 25 . (canceled)