Stacked package, method of fabricating stacked package, and method of mounting stacked package fabricated by the method

Abstract

Provided are a stacked package, a method of fabricating a stacked package, and a method of mounting the stacked package fabricated by the same. The method of fabricating a stacked package includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.

1 - 22 . (canceled) 
     
     
         23 . A stacked semiconductor package, comprising:
 an upper semiconductor package including an upper package substrate and one or more upper semiconductor chips formed on the upper package substrate, a first surface of the upper semiconductor package substrate including first bonding pads for connecting to outside the upper semiconductor package;   a lower semiconductor package including a lower package substrate and one or more lower semiconductor chips formed on the lower package substrate, a first surface of the lower semiconductor package substrate including second bonding pads for connecting to outside the lower semiconductor package; and   inter-package bonding units electrically and physically connecting the first bonding pads to respective ones of the second bonding pads,   wherein the inter-package bonding units include first solders having a first melting temperature in contact with first respective annealed solder paste nodes having a second melting temperature.   
     
     
         24 . The stacked semiconductor package of  claim 23 , further comprising:
 second solders disposed at a bottom surface of the lower package substrate, the second solders being annealed and having a melting temperature prior to annealing lower than the first and second melting temperatures; and   a package mounting board attached to the annealed second solders.   
     
     
         25 . The stacked semiconductor package of  claim 24 , further comprising:
 bonding pads at the bottom surface of the lower package substrate, the bonding pads corresponding to respective ones of the second solders and connected to the second solders.   
     
     
         26 . The stacked semiconductor package of  claim 23 , wherein:
 the upper package substrate is disposed between the one or more upper semiconductor chips and the lower package substrate, and one or more lower semiconductor chips are disposed between the upper package substrate and the lower package substrate.   
     
     
         27 . An inter-substrate bonding unit for electrically and physically connecting a first semiconductor substrate of a first semiconductor package to a second semiconductor substrate of a second semiconductor package, the inter-substrate bonding unit comprising:
 a first solder having a first melting temperature, the first solder connected to a bonding pad on a surface of the first semiconductor substrate; and   an annealed solder paste node having a second melting temperature, the annealed solder paste node connected to a bonding pad on a surface of the second semiconductor substrate and connected to the first solder, wherein   the annealed solder paste node has a melting temperature prior to annealing lower than the first melting temperature and lower than the second melting temperature.   
     
     
         28 . A stacked semiconductor package, comprising:
 an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature;   a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and transformed solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature higher than the first melting temperature, wherein the transformed solder paste nodes are interposed between the top surface of the lower package substrate and the first solders; and   second solders formed on a bottom surface of the lower package substrate and having a third melting temperature lower than the first and second melting temperature.   
     
     
         29 . The stacked semiconductor package of  claim 28 , wherein the first solders include an Sn—Sb based alloy or an Sn—Ag based alloy. 
     
     
         30 . The stacked semiconductor package of  claim 28 , wherein the transformed solder paste nodes include CuSn or CuSnAg. 
     
     
         31 . The stacked semiconductor package of  claim 28 , wherein the second solders include an Sn—Au—Cu based alloy. 
     
     
         32 . The stacked semiconductor package of  claim 28 , further comprising:
 a package mounting board attached to the second solders.   
     
     
         33 . A stacked semiconductor package, comprising:
 a package substrate;   semiconductor chips formed on a top surface of the package substrate;   first solders formed on a bottom surface of the package substrate and having a first melting temperature; and   transformed solder paste nodes interposed between the bottom surface of the package substrate and the first solders and having a second melting temperature higher than the first melting temperature.