Wiring board and method for manufacturing the same

Abstract

A semiconductor device includes a semiconductor chip and a wiring board formed on the semiconductor chip. The wiring board includes a first insulation layer, first conductive patterns on the first layer, first via conductors formed in the first layer and connecting the first patterns and electrode pads of the chip, respectively, a second insulation layer on the first layer, second conductive patterns on the second layer, and second via conductors formed in the second layer and connecting the first conductive patterns and the second patterns, respectively, each second via conductors has a side surface extending through the second layer such that the side surface has a bent portion which changes inclination of the side surface in depth direction of each second via conductor, and the second patterns are positioned to fan in or out with respect to the electrode pads.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor chip; and   a wiring board formed on the semiconductor chip,   wherein the wiring board comprises a first resin insulation layer, a plurality of first conductive patterns formed on the first resin insulation layer, a plurality of first via conductors formed in the first resin insulation layer such that the plurality of first via conductors is connecting the plurality of first conductive patterns and a plurality of electrode pads of the semiconductor chip, respectively, a second resin insulation layer formed on the first resin insulation layer, a plurality of second conductive patterns formed on the second resin insulation layer, and a plurality of second via conductors formed in the second resin insulation layer such that the plurality of second via conductors is connecting the plurality of first conductive patterns and the plurality of second conductive patterns, respectively, each of the second via conductors has a side surface extending through the second resin insulation layer such that the side surface has a bent portion which changes an inclination of the side surface in a depth direction of each of the second via conductors, and the plurality of second conductive patterns is positioned to fan in or out with respect to the plurality of electrode pads.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising a plurality of bump bodies formed on the plurality of second conductive patterns, respectively. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein each of the second via conductors tapers from the bent portion toward the first resin insulation layer such that the side surface of each of the second via conductor includes a tapered portion. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the plurality of second conductive patterns is positioned to fan out with respect to the plurality of electrode pads such that the plurality of second conductive patterns is positioned at a pitch which is wider than a pitch of the plurality of electrode pads. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the plurality of second conductive patterns is positioned in a peripheral form. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the plurality of second conductive patterns is positioned in an area-array form. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the second resin insulation layer is comprising a plurality of layers having different thermal expansion coefficients, and the plurality of layers forming the second resin insulation layer includes a first layer positioned closest to the first conductive patterns has a thermal expansion coefficient which is lower than a thermal expansion coefficient of a second layer positioned closest to the second conductive patterns. 
     
     
         8 . A semiconductor device, comprising:
 a semiconductor chip; and   a wiring board formed on the semiconductor chip,   wherein the wiring board comprises a resin insulation layer, a plurality of conductive patterns formed on the resin insulation layer, a plurality of via conductors connected to the plurality of conductive patterns, respectively, and a rewiring structures formed on the semiconductor chip and connecting the plurality of via conductors and a plurality of electrode pads of the semiconductor chip respectively, the plurality of conductive patterns is positioned to fan in or out with respect to the plurality of electrode pads, and each of the via conductors has a side surface extending through the resin insulation layer such that the side surface has a bent portion which changes an inclination of the side surface in a depth direction of each of the via conductors.   
     
     
         9 . The semiconductor device according to  claim 8 , further comprising a plurality of bump bodies formed on the plurality of conductive patterns, respectively. 
     
     
         10 . The semiconductor device according to  claim 8 , wherein each of the via conductors tapers from the bent portion toward the rewiring structures such that the side surface of each of the via conductors includes a tapered portion. 
     
     
         11 . The semiconductor device according to  claim 8 , wherein the plurality of conductive patterns is positioned to fan out with respect to the plurality of electrode pads such that the plurality of conductive patterns is positioned at a pitch which is wider than a pitch of the plurality of electrode pads. 
     
     
         12 . The semiconductor device according to  claim 8 , wherein the plurality of conductive patterns is positioned in a peripheral form. 
     
     
         13 . The semiconductor device according to  claim 8 , wherein the plurality of conductive patterns is positioned in an area-array form. 
     
     
         14 . The semiconductor device according to  claim 8 , wherein the resin insulation layer is comprising a plurality of layers having different thermal expansion coefficients, and the plurality of layers forming the resin insulation layer includes a first layer positioned closest to the rewiring structures has a thermal expansion coefficient which is lower than a thermal expansion coefficient of a second layer positioned closest to the conductive patterns. 
     
     
         15 . A method for manufacturing a semiconductor device, comprising:
 forming a first resin insulation layer on a semiconductor chip;   forming a plurality of first conductive patterns on the first resin insulation layer;   forming a plurality of second resin insulation layer on the first conductive patterns and the first resin insulation layer;   forming in the second resin insulation layer a plurality of opening portions extending to the plurality of first conductive patterns respectively such that each of the opening portions has a side wall having a bent portion which changes an inclination of the side surface in a depth direction of each of the opening portions;   forming in the plurality of opening portions of the second resin insulation layer a plurality of via conductors extending to the plurality of first conductive patterns such that each of the via conductors has a side surface having a bent portion which changes an inclination of the side surface in a depth direction of each of the via conductors; and   forming a plurality of second conductive patterns on the second resin insulation layer such that the second conductive patterns is formed on the plurality of via conductors respectively and positioned to fan in or out with respect to a plurality of electrode pads of the semiconductor chip.   
     
     
         16 . The method for manufacturing a semiconductor device according to  claim 15 , further comprising forming a plurality of bump bodies on the plurality of conductive patterns, respectively. 
     
     
         17 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the plurality of via conductors is formed to taper from the bent portion toward the first conductive patterns such that the side surface of each of the via conductors includes a tapered portion. 
     
     
         18 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the plurality of second conductive patterns is positioned to fan out with respect to the plurality of electrode pads such that the plurality of second conductive patterns is positioned at a pitch which is wider than a pitch of the plurality of electrode pads. 
     
     
         19 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the plurality of conductive patterns is positioned in a peripheral form or an area-array form. 
     
     
         20 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the forming of the second resin insulation layer comprises forming a plurality of layers having different thermal expansion coefficients such that the plurality of layers includes a first layer positioned closest to the first conductive patterns and having a thermal expansion coefficient which is lower than a thermal expansion coefficient of a second layer positioned closest to the conductive patterns.