Methods of manufacturing three-dimensional semiconductor devices

Abstract

Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

1 - 21 . (canceled) 
     
     
         22 . A three-dimensional semiconductor device,
 a first structure including a plurality of first gate patterns vertically stacked on a substrate;   a first active pattern passing through the first structure to contact the substrate;   a second structures including a plurality of second gate patterns vertically stacked on the first structure; and   a second active pattern passing through the second structure to contact the first active pattern;   wherein a top width of the first active pattern is greater than of a bottom width of the second active pattern.   
     
     
         23 . The device of  claim 22 , wherein a bottom width of the first active pattern is less than the top width of the first active pattern, and the first active patterns has a first inclined sidewall. 
     
     
         24 . The device of  claim 22 , wherein a top width of the second active pattern is greater than the bottom width of the second active pattern, and the second active patterns has a second inclined sidewall. 
     
     
         25 . The device of  claim 22 , wherein the uppermost one of the first gate patterns has a horizontal width which is less than that of the lowermost one of the second gate patterns. 
     
     
         26 . The device of  claim 22 , further comprising a data storage layer disposed between the first active pattern and the first gate patterns and between the second active pattern and the second gate patterns. 
     
     
         27 . A three-dimensional semiconductor device,
 a first structure including a plurality of first gate patterns vertically stacked on a substrate;   a second structures including a plurality of second gate patterns vertically stacked on the first structure; and   a plurality of active patterns passing through the first and the second structures to contact the substrate, each of the active patterns including a first portion disposed in the first structure and a second portion disposed in the second structure,   wherein a sidewall of each of the active patterns has an inflection point between the first portion and the second portion.   
     
     
         28 . The device of  claim 27 , wherein a width of the first portion gradually increases with increasing distance from the substrate, and a width of the second portion gradually increases with increasing distance from the substrate. 
     
     
         29 . The device of  claim 27 , wherein each of the active patterns has a discontinuous boundary surface between the first portion and the second portion. 
     
     
         30 . The device of  claim 27 , wherein the uppermost one of the first gate patterns has a horizontal width which is less than that of the lowermost one of the second gate patterns. 
     
     
         31 . The device of  claim 27 , wherein the active patterns are arranged in zigzag form along the one direction in a plan view. 
     
     
         32 . The device of  claim 27 , further comprising a data storage layer disposed between the active patterns and the first and the second gate patterns.