Method of forming a dram array of devices with vertically integrated recessed access device and digitline

Abstract

A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.

What is claimed is: 
     
         1 . A device, comprising:
 a substrate;   a wordline trench formed in the substrate; and   a digitline trench formed in the substrate, wherein the digitline trench is substantially perpendicular to the wordline trench and formed substantially beneath the wordline trench, and wherein the wordline trench and the digitline trench are each formed below a surface of the substrate.   
     
     
         2 . The device of  claim 1 , comprising a digitline disposed inside the digitline trench. 
     
     
         3 . The device of  claim 1 , comprising a wordline disposed inside the wordline trench. 
     
     
         4 . The device of  claim 1 , comprising a digitline contact formed inside a single-sided opening of the digitline trench, wherein the digitline contact is configured to electrically couple the substrate to a digitline formed inside the digitline trench. 
     
     
         5 . The device of  claim 4 , wherein the single-sided opening of the digitline trench comprises a sidewall, and wherein a single-sided contact is formed substantially between the sidewall and the digitline. 
     
     
         6 . The device of  claim 1 , wherein the wordline trench and the digitline trench are each formed below an upper surface of the substrate and above a lower surface of the substrate. 
     
     
         7 . The device of  claim 1 , wherein the digitline trench is formed at a depth substantially beneath the bottom of the wordline trench. 
     
     
         8 . The device of  claim 1 , comprising a gate electrode formed above the wordline trench and the digitline trench, wherein the gate electrode comprises a plurality gapped regions along a first direction and a plurality of pinched regions along a second direction. 
     
     
         9 . The device of  claim 8 , wherein gate electrode comprises a continuous gate electrode along the direction of the wordline trench and a discontinuous gate electrode along the direction of the digitline trench. 
     
     
         10 . The device of  claim 1 , comprising a contact formed vertically above the wordline trench and the digitline trench. 
     
     
         11 . A method of manufacturing a device, comprising:
 forming an access line trench recessed below a surface of a substrate;   forming a data line trench recessed below the access line trench, wherein the data line trench extends along one or more directions perpendicular to the access line trench, and wherein an intersection of the access line trench and the data line trench forms a plurality of pillars extending from the substrate;   forming a word line inside the access line trench;   forming a data line inside the data line trench; and   forming a contact with an upper portion of each of the plurality of pillars.   
     
     
         12 . The method of  claim 11 , wherein forming the plurality of pillars comprises defining respective depths of the access line trench and the data line trench. 
     
     
         13 . The method of  claim 11 , comprising forming the data line before formation of a gate electrode of the device. 
     
     
         14 . The method of  claim 13 , comprising removing one or more portions of the gate electrode to form a discontinuous gap in the gate electrode between each pillar of the plurality of pillars along a direction of the data line trench. 
     
     
         15 . The method of  claim 11 , wherein forming the plurality of pillars comprises defining a width of each pillar of the plurality of pillars in the direction of the access line trench in relation to the width of the access line trench, and defining a width of each pillar of the plurality of pillars in the direction of the data line trench in relation to the width of the data line trench. 
     
     
         16 . The method of  claim 11 , comprising forming a plurality of data lines by depositing a conductive material inside a plurality of data line trenches and etching a portion of the conductive material to a determinable depth within the plurality of data line trenches. 
     
     
         17 . A memory device, comprising:
 a plurality of wordline trenches extending along a first path at a first depth below an upper surface of a substrate;   a plurality of digitline trenches extending along a second path at a second depth below the upper surface of the substrate, wherein the first path is substantially perpendicular to the second path, and wherein the second depth is greater than the first depth; and   a plurality of cell contacts formed vertically above the plurality of wordline trenches and the plurality of digitline trenches, wherein the plurality of cell contacts is configured to electrically couple to the substrate.   
     
     
         18 . The memory device of  claim 17 , wherein a width of the plurality of wordline trenches is greater than a width of the plurality of digitline trenches. 
     
     
         19 . The memory device of  claim 17 , wherein the plurality of wordline trenches comprises a plurality of wordlines disposed along a bottom area of the plurality of wordline trenches, and wherein the plurality of digitline trenches comprises a plurality of digitlines disposed along a bottom area of the plurality of digitline trenches. 
     
     
         20 . The memory device of  claim 17 , comprising a gate electrode, wherein the gate electrode comprises a plurality of gaps along the path of the plurality of digitline trenches and does not comprise the plurality of gaps along the path of the plurality of wordline trenches.