Semiconductor device having gate trench and manufacturing method thereof

Abstract

Disclosed herein is a semiconductor device that includes a trench formed across active regions and the element isolation regions. A conductive film is formed at a lower portion of the trench, and a cap insulating film is formed at an upper portion of the trench. The cap insulating film has substantially the same planer shape as that of the conductive film.

What is claimed is: 
     
         1 . A manufacturing method of a semiconductor device, the method comprising:
 forming a plurality of element isolation regions extending in a first direction in parallel on a semiconductor substrate so that a plurality of active regions each sandwiched between adjacent two of the element isolation regions are defined in the semiconductor substrate, each of the element isolation regions having an element isolation insulating film filling an isolation trench formed in the semiconductor substrate, and the active regions being arranged at a predetermined pitch in a second direction intersecting with the first direction;   forming a plurality of gate trenches extending in the second direction across the element isolation regions and the active regions, each of the gate trenches having a plurality of first trench portions crossing the active regions and a plurality of second trench portions crossing the element isolation regions, the first trench portions having bottom surfaces positioned at higher than bottom surfaces of the second trench portions so that each of the active regions have a plurality of first fin portions formed on the bottom surfaces of the first trench portions protruding with respect to the bottom surfaces of the second trench portions, and the second trench portions having a width in the first direction wider than a width of the first trench portions in the first direction so that each of the active regions have a plurality of second fin portions formed on side surfaces of the first trench portions protruding with respect to the side surfaces of the second trench portions;   forming a plurality of conductive films each buries a lower portion of an associated one of the gate trenches; and   forming a plurality of cap insulating films each covers an upper surface of an associated one of the conductive films so that the cap insulating films bury upper portions of the gate trenches.   
     
     
         2 . The manufacturing method of the semiconductor device as claimed in  claim 1 , wherein the forming the trench portions includes:
 forming first openings extending in the second direction across the element isolation regions and the active regions by an anisotropic dry etching method so that the bottom and side surfaces of the first and second trenches are exposed; and   etching the bottom and side surfaces of the second trenches by isotropic etching method.   
     
     
         3 . The manufacturing method of the semiconductor device as claimed in  claim 2 , wherein the forming the first openings includes:
 forming a plurality of mask films extending in the second direction across the element isolation regions and the active regions; and   etching the element isolation regions and the active regions using the mask films as an etching mask so that the first openings are formed.   
     
     
         4 . The manufacturing method of the semiconductor device as claimed in  claim 3 , wherein the mask films comprise substantially the same material as the element isolation insulating films. 
     
     
         5 . The manufacturing method of the semiconductor device as claimed in  claim 4 , wherein the mask films and the element isolation insulating films comprise a silicon dioxide. 
     
     
         6 . The manufacturing method of the semiconductor device as claimed in  claim 3 , wherein the mask films comprise different material from the cap insulating films. 
     
     
         7 . The manufacturing method of the semiconductor device as claimed in  claim 6 , wherein the mask films comprise a silicon dioxide, and the cap insulating films comprise a silicon nitride. 
     
     
         8 . The manufacturing method of the semiconductor device as claimed in  claim 1 , wherein the conductive films and the cap insulating films fill the gate trenches. 
     
     
         9 . A manufacturing method of a semiconductor device, the method comprising:
 forming first and second element isolation regions extending in a first direction in a semiconductor substrate so that an active region of the semiconductor substrate sandwiched between the first and second element isolation regions in a second direction intersecting with the first direction is defined;   forming first and second films extending in the second direction over the first and second element isolation regions and the active region, each of the first and second films having a lower film and an upper film;   anisotropic etching the first and second element isolation regions and the active region using the upper films as an etching mask so that a first trench portion is formed in the active region and second trench portions are formed in the first and second element isolation regions;   removing the upper films so that the lower films are exposed; and   isotropic etching the first and second element isolation regions and the lower films so that a first fin portion is formed on a bottom surface of the first trench portions protruding with respect to bottom surfaces of the second trench portions, and so that second fin portions are formed on side surfaces of the first trench portions protruding with respect to side surfaces of the second trench portions.   
     
     
         10 . The manufacturing method of the semiconductor device as claimed in  claim 9 , the method further comprising forming a conductive film in the first and second trench portions. 
     
     
         11 . The manufacturing method of the semiconductor device as claimed in  claim 10 , wherein the conductive film has an upper surface that is positioned lower than upper surfaces of the first and second element isolation regions. 
     
     
         12 . The manufacturing method of the semiconductor device as claimed in  claim 11 , the method further comprising forming a cap insulating film on the conductive film. 
     
     
         13 . The manufacturing method of the semiconductor device as claimed in  claim 12 , wherein the cap insulating film has an upper surface that is positioned at substantially the same plane as the upper surfaces of the first and second element isolation regions. 
     
     
         14 . The manufacturing method of the semiconductor device as claimed in  claim 12 , wherein the cap insulating film has substantially the same planer shape as that of the conductive film. 
     
     
         15 . The manufacturing method of the semiconductor device as claimed in  claim 9 , wherein the lower films comprise substantially the same material as the first and second element isolation regions. 
     
     
         16 . The manufacturing method of the semiconductor device as claimed in  claim 15 , wherein the lower films and the first and second element isolation regions comprise a silicon dioxide. 
     
     
         17 . The manufacturing method of the semiconductor device as claimed in  claim 12 , wherein the lower films comprise a silicon dioxide, and the cap insulating film comprising a silicon nitride. 
     
     
         18 . The manufacturing method of the semiconductor device as claimed in  claim 12 , wherein the upper films comprise neither a silicon dioxide nor a silicon nitride. 
     
     
         19 . The manufacturing method of the semiconductor device as claimed in  claim 10 , the method further comprising forming a gate insulating film between the conductive film and the first and second fin portions. 
     
     
         20 . The manufacturing method of the semiconductor device as claimed in  claim 19 , wherein the conductive film serves as a gate electrode of a field effect transistor, and the first and second fin portions serve as a channel region of the field effect transistor.