Clock signal generation apparatus for use in semiconductor memory device and its method

Abstract

A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

What is claimed is: 
     
         1 . A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, comprising:
 a clock signal generation unit for receiving the external clock signal to generate the reference clock signal in response to a control signal; and   a control unit for generating the control signal based on a read command, a write command and an external address, wherein the write command is inactivated when a read command is inputted.   
     
     
         2 . A method for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, the method comprising the steps of:
 generating a control signal based on a read command, a write command and an external address; and   generating the reference clock signal based on an internal clock signal in response to the control signal, wherein the write command is inactivated when a read command is inputted.   
     
     
         3 . A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, comprising:
 a clock signal generation unit for receiving the external clock signal to generate the reference clock signal in response to a control signal; and   a control unit for generating the control signal based on a read command, a write command and an external address, wherein the control signal is in an activated state for a predetermined time after the control signal is activated in response to the read command, wherein the predetermined time corresponds to a value of adding a predetermined delay time and a burst length (BL) to a column address strobe (CAS) latency, and wherein the write command is inactivated when a read command is inputted.