US2014225902A1PendingUtilityA1

Image pyramid processor and method of multi-resolution image processing

Assignee: NVIDIA CORPPriority: Feb 11, 2013Filed: Feb 11, 2013Published: Aug 14, 2014
Est. expiryFeb 11, 2033(~6.6 yrs left)· nominal 20-yr term from priority
G06T 1/20G06T 1/60G06T 1/00
41
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Claims

Abstract

An image pyramid processor and a method of multi-resolution image processing. One embodiment of the image pyramid processor includes: (1) a level multiplexer configured to employ a single processing element to process multiple levels of an image pyramid in a single work unit, and (2) a buffer pyramid having memory allocable to store respective intermediate results of the single work unit.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An image pyramid processor, comprising:
 a level multiplexer configured to employ a single processing element to process multiple levels of an image pyramid in a single work unit; and   a buffer pyramid having memory allocable to store respective intermediate results of said single work unit.   
     
     
         2 . The image pyramid processor recited in  claim 1  wherein said buffer pyramid is allocable in static random access memory. 
     
     
         3 . The image pyramid processor recited in  claim 1  wherein said level multiplexer employs a timing multiplexer. 
     
     
         4 . The image pyramid processor recited in  claim 1  wherein said image pyramid comprises three successively higher resolution levels. 
     
     
         5 . The image pyramid processor recited in  claim 1  wherein said single work unit includes a pixel and each sub-pixel composing said pixel at said multiple levels of said image pyramid. 
     
     
         6 . The image pyramid processor recited in  claim 1  wherein said single processing element carries out an atomic computer vision function. 
     
     
         7 . The image pyramid processor recited in  claim 6  wherein said atomic computer vision function is a convolution function. 
     
     
         8 . A method of multi-resolution image processing, comprising:
 carrying out an operation on a first resolution level pixel of an image pyramid during a first processing cycle and storing results in a pyramid buffer; and   employing said results in carrying out said operation on a second resolution level pixel related to said first resolution level pixel during a second processing cycle.   
     
     
         9 . The method recited in  claim 8  wherein said first resolution level pixel is a higher resolution pixel relative to said second resolution level pixel. 
     
     
         10 . The method recited in  claim 9  wherein said second resolution level pixel is a lower resolution pixel and comprises four sub-pixels, one of which is said higher resolution pixel. 
     
     
         11 . The method recited in  claim 8  further comprising:
 storing second resolution level results of carrying out said operation on said second resolution level pixel in said pyramid buffer; and 
 employing said second resolution level results in carrying out said operation on a third resolution level pixel related to said second resolution level pixel during a third processing cycle. 
 
     
     
         12 . The method recited in  claim 8  wherein said first processing cycle and said second processing cycle are of equal duration. 
     
     
         13 . The method recited in  claim 8  further comprising allocating said pyramid buffer in static random access memory. 
     
     
         14 . The method recited in  claim 8  wherein said carrying out said operation includes performing a motion estimation. 
     
     
         15 . A computer vision engine, comprising:
 a processing engine pool having a processing element operable to carry out an operation on pixels within a multi-level work unit of an image pyramid;   a control block configured to direct said processing element to process said multi-level work unit completely before processing another multi-level work unit; and   a buffer pyramid configured to store respective intermediate results generated by said processing element.   
     
     
         16 . The computer vision engine recited in  claim 15  wherein said multi-level work unit comprises:
 a single pixel at a first resolution level; 
 four pixels at a second resolution level; and 
 sixteen pixels at a third resolution level. 
 
     
     
         17 . The computer vision engine recited in  claim 15  wherein said control block is operable to direct said processing element to:
 retrieve said intermediate results of a higher resolution level from said buffer pyramid; and 
 employ said intermediate results to process a lower resolution level within said multi-level work unit. 
 
     
     
         18 . The computer vision engine recited in  claim 15  further comprising a main memory configured to store input image pyramid data employable to process a lowest resolution level of said image pyramid and output image pyramid data generated by processing a highest resolution level of said image pyramid. 
     
     
         19 . The computer vision engine recited in  claim 15  wherein said pyramid buffer is allocable in static random access memory (SRAM). 
     
     
         20 . The computer vision engine recited in  claim 15  wherein said operation is an addition function.

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