Delay Locked Loop Circuit and Method

Abstract

A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

What is claimed is: 
     
         1 . A delay locked loop for providing a delay clock signal, the delay locked loop comprising:
 a phase detector for detecting a phase difference between a reference clock signal and the delay clock signal;   an initialization control circuit coupled to an output of the phase detector for providing an inversion control signal;   an inverting circuit including a multiplexer, the inverting circuit being connected to the inversion control signal for providing a single one of the reference clock signal and a phase-shifted reference clock signal; and   a variable delay line having an output coupled to the inverting circuit.