Interposer chip, multi-chip package including the interposer chip, and method of manufacturing the same

Abstract

An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.

1 - 10 . (canceled) 
     
     
         11 . A multi-chip package comprising:
 a package substrate;   a first semiconductor chip and a second semiconductor chip arranged over the package substrate; and   an interposer chip arranged between each of the first and second semiconductor chips and the package substrate,   wherein the interposer chip comprises:   a substrate;   a plurality of upper terminals at a first surface of the substrate, at least one upper terminal comprising an external connection for connecting outside the interposer chip;   a plurality of lower terminals at a second surface, opposite surface of the substrate, at least one lower terminal comprising an external connection for connecting outside the interposer chip;   for a first upper terminal, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals;   for a second upper terminal, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals; and   a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.   
     
     
         12 . The multi-chip package of  claim 11 , wherein each of the first conductive pattern and second conductive pattern comprises one or more plug pattern. 
     
     
         13 . The multi-chip package of  claim 12 , wherein one or more plug pattern comprising:
 a first plug pattern formed through the substrate and fill with a conductive material in a first through-substrate via for electrically connecting to the first conductive pattern; and   a second plug formed through the substrate and fill with the conductive material in a second through-substrate via for electrically connecting to the second conductive pattern.   
     
     
         14 . The multi-chip package of  claim 11 , wherein the test pattern comprises a third conductive pattern composed of the same material as the first and second conductive patterns. 
     
     
         15 . The multi-chip package of  claim 11 , wherein the test pattern comprises an e-fuse pattern including a transistor. 
     
     
         16 . The multi-chip package of  claim 11 , wherein the first semiconductor chip, the second semiconductor chip and the package substrate are electrically connected through the interposer chip. 
     
     
         17 . The multi-chip package of  claim 16 , further comprising:
 a third plug and fourth plug formed through the package substrate, the third and fourth plugs electrically connected with the first conductive pattern and the second conductive pattern of the interposer chip, respectively.   
     
     
         18 . The multi-chip package of  claim 17 , further comprising:
 a first conductive bump contacted the first and third plugs and arranged between the first plug and third plug; and   a second conductive bump contacted the second and fourth plugs and arranged between the second plug and fourth plug.   
     
     
         19 . The multi-chip package of  claim 18 , further comprising:
 a third conductive bump contacted the first conductive pattern and arranged between the first semiconductor chip and the interposer chip; and   a fourth conductive bump contacted the second conductive pattern and arranged between the second semiconductor chip and the interposer chip.   
     
     
         20 . A multi-chip package comprising:
 a package substrate;   a first semiconductor chip disposed over the package substrate;   a second semiconductor chip disposed at the same level of the first semiconductor chip and disposed over the package substrate; and   an interposer chip disposed between the first and second semiconductor chips and the package substrate,   wherein the interposer chip comprises:   a silicon substrate;   a first conductive pattern disposed in the silicon substrate;   a second conductive pattern disposed in the silicon substrate; and   a test pattern connected between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern,   wherein the test pattern is cut by applying current after testing, and   wherein the test pattern includes a cut fuse.