Semiconductor memory device

Abstract

Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in.

1 - 3 . (canceled) 
     
     
         4 . A method for erasing data from a plurality of non-volatile memory circuit comprising:
 receiving at a first non-volatile memory a data erase operation command, the first non-volatile memory being one of the plurality of non-volatile memory circuits;   erasing the first non-volatile memory in accordance with the data erase operation request;   outputting for the first non-volatile memory a completion signal when the data erase operation of the first non-volatile memory is completed; and   repeating the erasing and outputting for others of the plurality of non-volatile memory circuits for which the data erase operation has not been processed.   
     
     
         5 . The method of  claim 4 , wherein data in the plurality of non-volatile memory circuits is erased in response to the erase operation command. 
     
     
         6 . The method of  claim 5 , wherein the data erase operation command is executed sequentially across the plurality of non-volatile memory circuits. 
     
     
         7 . The method of  claim 4 , wherein the completion signal outputted from the first non-volatile memory is used to start an erase operation for a second non-volatile memory. 
     
     
         8 . The method of  claim 4 , wherein the local completion signal outputted from the first non-volatile memory is latched to a second non-volatile memory. 
     
     
         9 . The method of  claim 4 , further comprising detecting completion of the data erase operation command for the plurality of non-volatile memory circuits based on receiving a local completion signal from a last non-volatile memory. 
     
     
         10 . The method of  claim 9 , wherein the last non-volatile memory is a last of the plurality of memory circuits to erase data per erase operation command. 
     
     
         11 . A memory system comprising:
 a plurality of non-volatile memory circuits;   a controller configured to issue a data erase operation command to a first non-volatile memory being one of the plurality of non-volatile memory circuits;   circuitry configured to erase the first non-volatile memory in accordance with the data erase operation request;   a shift circuit configured to output a completion signal when the data erase operation of the first non-volatile memory is completed; and   repeating the erasing and outputting for others of the plurality of non-volatile memory circuits for which the data erase operation has not been processed.   
     
     
         12 . The memory system of  claim 11 , wherein data in the plurality of non-volatile memory circuits is erased in response to the erase operation command. 
     
     
         13 . The memory system of  claim 12 , wherein the data erase operation command is executed sequentially across the plurality of non-volatile memory circuits. 
     
     
         14 . The memory system of  claim 11 , wherein the completion signal outputted from the first non-volatile memory is used to start an erase operation for a second non-volatile memory. 
     
     
         15 . The memory system of  claim 11 , wherein the local completion signal outputted from the first non-volatile memory is latched to a second non-volatile memory. 
     
     
         16 . The memory system of  claim 11 , further comprising detecting completion of the data erase operation command for the plurality of non-volatile memory circuits based on receiving a local completion signal from a last non-volatile memory. 
     
     
         17 . The memory system of  claim 16 , wherein the last non-volatile memory is a last of the plurality of memory circuits to erase data per erase operation command.