Multi-layer barrier layer for interconnect structure

Abstract

A semiconductor device includes a dielectric layer positioned above a substrate of the semiconductor device and a recess defined in the dielectric layer. An adhesion barrier layer is positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the adhesion barrier layer directly contacts the dielectric layer. A stress-reducing barrier layer is positioned adjacent to the adhesion barrier layer, wherein the stress-reducing barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level. At least one layer of a conductive fill material is positioned over the stress-reducing barrier layer, the at least one layer of the conductive fill material substantially filling the recess.

1 .- 21 . (canceled) 
     
     
         22 . A semiconductor device, comprising:
 a dielectric layer positioned above a substrate of said semiconductor device;   a recess defined in said dielectric layer;   an adhesion barrier layer positioned on and in direct contact with at least sidewalls of said recess, a barrier layer interface being defined where said adhesion barrier layer directly contacts said dielectric layer;   a stress-reducing barrier layer positioned adjacent to said adhesion barrier layer, wherein said stress-reducing barrier layer is adapted to reduce a stress level across said barrier layer interface from a first stress level to a second stress level that is less than said first stress level; and   at least one layer of a conductive fill material positioned over said stress-reducing barrier layer, said at least one layer of said conductive fill material substantially filling said recess.   
     
     
         23 . The semiconductor device of  claim 22 , wherein said stress-reducing barrier layer comprises an alloy of tantalum and a first transition metal other than tantalum. 
     
     
         24 . The semiconductor device of  claim 23 , wherein said first transition metal comprises titanium. 
     
     
         25 . The semiconductor device of  claim 23 , further comprising a wetting layer positioned between said stress-reducing barrier layer and said at least one layer of said conductive fill material, said wetting layer comprising an alloy of said first transition metal and a second transition metal other than tantalum. 
     
     
         26 . The semiconductor device of  claim 25 , wherein said first transition metal comprises titanium and said second transition metal comprises ruthenium. 
     
     
         27 . The semiconductor device of  claim 22 , wherein said at least said one layer of said conductive fill material comprises copper. 
     
     
         28 . The semiconductor device of  claim 22 , wherein said at least one layer of said conductive fill material comprises first and second seed layers positioned adjacent to said stress-reducing barrier layer. 
     
     
         29 . The semiconductor device of  claim 28 , wherein said first seed layer is positioned between said second seed layer and said stress-reducing barrier layer and said second seed layer is a doped seed layer comprising a dopant that is not present in said first seed layer. 
     
     
         30 . The semiconductor device of  claim 29 , wherein said dopant comprises manganese. 
     
     
         31 . The semiconductor device of  claim 22 , wherein said adhesion barrier layer comprises tantalum. 
     
     
         32 . The semiconductor device of  claim 22 , wherein said recess comprises at least one of a trench and a via opening. 
     
     
         33 . A semiconductor device, comprising:
 a dielectric layer positioned above a substrate of said semiconductor device;   a recess defined in said dielectric layer;   a first barrier layer positioned on and in direct contact with at least sidewalls of said recess, a barrier layer interface being defined where said first barrier layer directly contacts said dielectric layer;   a second barrier layer positioned adjacent to said first barrier layer, wherein said second barrier layer is adapted to reduce a stress level across said barrier layer interface from a first stress level to a second stress level that is less than said first stress level, said second barrier layer comprising tantalum and a first transition metal other than tantalum;   a wetting layer positioned adjacent to said second barrier layer, said wetting layer comprising an alloy of said first transition metal and a second transition metal other than tantalum; and   at least one layer of conductive material filling said recess, wherein said wetting layer is positioned between said second barrier layer and said at least one layer of conductive material.   
     
     
         34 . The semiconductor device of  claim 33 , wherein said first transition metal comprises titanium. 
     
     
         35 . The semiconductor device of  claim 33 , wherein said second transition metal comprises ruthenium. 
     
     
         36 . The semiconductor device of  claim 33 , wherein said at least one layer of conductive material comprises copper. 
     
     
         37 . The semiconductor device of  claim 33 , wherein said at least one layer of conductive material comprises a doped seed layer and a layer of bulk fill material positioned on and in direct contact with said doped seed layer, said doped seed layer comprising manganese and said layer of bulk fill material comprising copper.