Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions

Abstract

Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device that includes a first substrate region and a second substrate region, comprising:
 disposing a gate layer on the first and second substrate regions;   forming a first gate in the first substrate region from the gate layer;   forming a second gate in the second substrate region from the gate layer;   forming first source and drain regions substantially adjacent to the second gate;   forming a third gate in the second substrate region from the gate layer; and   forming second source and drain regions, substantially adjacent to the third gate,   wherein the second source and drain regions are of complementary conductivity type to the first source and drain regions, and wherein the third gate is formed after the first source and drain regions are formed.   
     
     
         2 . The method of  claim 1 , further comprising forming the first gate after the second and third gates. 
     
     
         3 . The method of  claim 1 , further comprising forming the second substrate region as a high voltage substrate region. 
     
     
         4 . The method of  claim 1 , further comprising forming the first source and drain regions as lightly doped drains. 
     
     
         5 . The method of  claim 1 , further comprising disposing polycrystalline silicon as the gate layer. 
     
     
         6 . The method of  claim 1 , further comprising disposing metal as the gate layer, or a poly layer for sacrificial gate to be replaced by metal gate later in the flow. 
     
     
         7 . The method of  claim 1 , further comprising forming the first substrate region as a low voltage substrate region, or a memory substrate region, or a combination of memory and low voltage regions. 
     
     
         8 . The method of  claim 1 , further comprising forming the first gate, the second gate and the third gate as having the same physical thickness and material. 
     
     
         9 . The method of  claim 1 , further comprising forming a shallow trench isolation between the first and second substrate regions. 
     
     
         10 . The method of  claim 1 , further comprising disposing a mask to define the second gate, and removing the mask after forming the first source and drain regions. 
     
     
         11 . The method of  claim 1 , further comprising disposing a resist on at least one of the first gate and the third gate before forming the first source and drain regions and leaving the resist in place until the first source and drain regions have been formed. 
     
     
         12 . A semiconductor device having a first substrate region and a second substrate region, comprising:
 a first gate in the first substrate region;   a second gate in the second substrate region;   a third gate in the second substrate region;   first source and drain regions substantially adjacent to the second gate; and   second source and drain regions, substantially adjacent to the third gate,   wherein the second source and drain regions are of a complementary conductivity type to the first source and drain regions, the second gate and the third gate are configured to withstand the same amount of voltage, which is more than the first gate is configured to withstand; and   the first drain region is older than the third gate.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the second and third gates comprise high voltage gates. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the first source and drain regions comprise lightly doped drains. 
     
     
         15 . The semiconductor device of  claim 12 , wherein the second gate comprises polycrystalline silicon. 
     
     
         16 . The semiconductor device of  claim 12 , wherein the second gate comprises metal. 
     
     
         17 . The semiconductor device of  claim 12 , Wherein the first gate comprises a logic gate, or a memory substrate region, or a combination of memory and low voltage regions. 
     
     
         18 . The semiconductor device of  claim 12 , wherein the first gate, the second gate and the third gate each have the same physical thickness and material. 
     
     
         19 . The semiconductor device of  claim 12 , further comprising a shallow trench isolation. between the first and second substrate regions. 
     
     
         20 . A method of manufacturing a semiconductor device that includes a first substrate region and a second substrate region, comprising:
 disposing a thin poly layer on the first and second substrate regions;   forming a first gate in the first substrate region from the thin poly layer;   disposing a first photoresist mask on the thin poly layer, across both the first substrate region and the second substrate region;   etching a second gate in the second substrate region through the first photoresist mask;   performing a first high energy implant through the first photoresist mask while the photoresist mask protects the poly in both the first and second substrate regions;   removing the first photoresist mask;   disposing a second photoresist mask on the thin poly layer, across both the first substrate region and the second substrate region;   etching a third gate in the second substrate region through the second photoresist mask;   performing a second high energy implant through the second photoresist mask while the photoresist mask protects the poly in both the first and second substrate regions; and   removing the second photoresist mask.