Semiconductor device and manufacturing method of semiconductor device

Abstract

A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

1 - 22 . (canceled) 
     
     
         23 . A semiconductor device, comprising:
 a semiconductor substrate;   a first gate electrode disposed over the semiconductor substrate;   a second gate electrode disposed over the semiconductor substrate so as to be adjacent to the first gate electrode;   a first insulating film formed between the first gate electrode and the semiconductor substrate;   a second insulating film formed between the second gate electrode and the semiconductor substrate, and between the first gate electrode and the second gate electrode, the second insulating film including a charge storing portion;   a drain region disposed in the semiconductor substrate on the first gate electrode side, the drain region including a high concentration impurity diffusion layer and a first low concentration impurity diffusion layer; and   a source region disposed in the semiconductor substrate on the second gate electrode side, the source region including a second low concentration impurity diffusion layer,   wherein the source region has no impurity diffusion layer with an impurity concentration higher than that of the second low concentration impurity diffusion layer.   
     
     
         24 . The semiconductor device according to  claim 23 ,
 wherein the first gate electrode contains n-type impurities,   wherein the second gate electrode contains p-type impurities, and   wherein the drain region and the source region contain n-type impurities.   
     
     
         25 . The semiconductor device according to  claim 23 ,
 wherein the first gate electrode is n-type,   wherein the second gate electrode is p-type, and   wherein the drain region and the source region are n-type.   
     
     
         26 . The semiconductor device according to  claim 23 ,
 wherein the second gate electrode includes:   a first silicon region positioned over the second insulating film; and   a second silicon region positioned over the first silicon region,   wherein the second silicon region contains p-type impurities, and   wherein a concentration of p-type impurities in the first silicon region is lower than a concentration of p-type impurities in the second silicon region.   
     
     
         27 . The semiconductor device according to  claim 26 ,
 wherein the second insulating film and the first silicon region of the second gate electrode intervene between the semiconductor substrate and the second silicon region of the second gate electrode, and   wherein the second insulating film and the first silicon region of the second gate electrode intervene in between the first gate electrode and the second silicon region of the second gate electrode.   
     
     
         28 . The semiconductor device according to  claim 26 ,
 wherein the first silicon region is a p-type impurity region having a concentration of p-type impurities lower than that of the second silicon region.   
     
     
         29 . The semiconductor device according to  claim 26 ,
 wherein the first silicon region is an n-type impurity region having a concentration of n-type impurities lower than that of the second silicon region.   
     
     
         30 . The semiconductor device according to  claim 26 ,
 wherein the first silicon region is a region not containing any impurities.   
     
     
         31 . The semiconductor device according to  claim 24 , further including a silicon film disposed over the source region,
 wherein the silicon film contains n-type impurities at a concentration higher than that of the second low concentration impurity diffusion layer.   
     
     
         32 . The semiconductor device according to  claim 31 , further including a first metal silicide film disposed over the silicon film. 
     
     
         33 . The semiconductor device according to  claim 32 ,
 wherein a metal silicide film is not disposed on the second low concentration impurity diffusion layer.   
     
     
         34 . The semiconductor device according to  claim 33 , further including a second metal silicide film disposed over the high concentration impurity diffusion layer and a third metal silicide film disposed over the second low concentration impurity diffusion layer.