Semiconductor device comprising a passive component of capacitors and process for fabrication

Abstract

A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

What is claimed is: 
     
         1 . A process for fabricating a semiconductor device, comprising:
 placing, in at least one location on a receiving surface of a carrier, an electrical connection frontside of at least one integrated circuit chip and a frontside of at least one passive component comprising at least one conductive plate and a dielectric plate for forming a capacitor;   forming on the receiving surface a layer of an encapsulation material so as to obtain, in the location, a wafer comprising an encapsulation block in which the chip and the passive component are embedded and having a frontside comprising the frontside of the chip and the frontside of the passive component;   then selectively connecting the at least one conductive plate to the chip, so that the capacitor is connected to the chip.   
     
     
         2 . The process according to  claim 1 , further comprising forming at least one front electrical connection track on the frontside of the wafer. 
     
     
         3 . The process according to  claim 2 , further comprising:
 forming at least one back electrical connection track on the backside of the wafer; and   forming an electrical connection via through the wafer and forming a front electrical connection track on the frontside of the wafer, the back track and the front track being connected by the electrical connection via.   
     
     
         4 . The process according to  claim 1 , further comprising placing the passive component such that the at least one conductive plate extends perpendicular to the receiving surface, then selectively connecting an edge of the at least one conductive plate to the chip. 
     
     
         5 . The process according to  claim 1 , further comprising placing the passive component such that the at least one plate extends parallel to the receiving surface. 
     
     
         6 . The process according to  claim 5 , further comprising:
 placing the passive component having a dielectric plate on the receiving surface; and   forming at least one additional conductive plate on the frontside of this dielectric plate so as to form the capacitor comprising the additional conductive plate and the at least one conductive plate separated by the first dielectric plate.   
     
     
         7 . A process comprising:
 placing an electrical connection frontside of an integrated circuit chip on a receiving surface of a carrier;   placing a capacitive structure comprising at least one conductive plate and at least one dielectric plate on the receiving surface of the carrier adjacent to the integrated circuit chip;   providing an encapsulating material layer surrounding the integrated circuit chip and the capacitive structure, the encapsulating material layer having a backside co-planar with a backside of the integrated circuit chip;   forming an electrical connection between the electrical connection frontside of the integrated circuit chip and the at least one conductive plate of the capacitive structure, the electrical connection comprising a via passing through the encapsulating material layer and a connection line formed on the backside of the encapsulating material layer.   
     
     
         8 . The process of  claim 7 , wherein placing the capacitive structure comprises orienting the at least one conductive plate parallel to the receiving surface of the carrier. 
     
     
         9 . The process of  claim 8 , wherein forming the electrical connection further comprises another via passing through the encapsulating material layer between the connection line formed on the backside of the encapsulating material layer and the at least one conductive plate. 
     
     
         10 . The process of  claim 9 , further comprising:
 removing the carrier, the electrical connection frontside of the integrated circuit chip being co-planar with a frontside of the encapsulating material layer;   forming another conductive plate and another electrical connection between the electrical connection frontside of the integrated circuit chip and the another conductive plate, the another electrical connection comprising a connection line formed on the frontside of the encapsulating material layer.   
     
     
         11 . The process of  claim 7 , wherein placing the capacitive structure comprises orienting the at least one conductive plate perpendicular to the receiving surface of the carrier. 
     
     
         12 . The process of  claim 11 , wherein forming the electrical connection further comprises making an electrical connection between the connection line formed on the backside of the encapsulating material layer and an edge of the at least one conductive plate. 
     
     
         13 . The process of  claim 12 , wherein the capacitive structure comprises an another conductive plate oriented perpendicular to the receiving surface of the carrier, further comprising:
 removing the carrier, the electrical connection frontside of the integrated circuit chip being co-planar with a frontside of the encapsulating material layer;   forming another electrical connection between the electrical connection frontside of the integrated circuit chip and the another conductive plate, the another electrical connection comprising a connection line formed on the frontside of the encapsulating material layer.   
     
     
         14 . The process of  claim 13 , wherein forming the another electrical connection further comprises making an electrical connection between the connection line formed on the frontside of the encapsulating material layer and an edge of the another conductive plate. 
     
     
         15 . A method for fabricating a device having a passive component having at least one capacitor, the method comprising:
 placing a frontside of an integrated circuit chip and a frontside of the capacitor in at least one location on a receiving surface of a carrier;   encapsulating the receiving surface, the integrated circuit chip, and the capacitor in an encapsulation layer to define an encapsulated structure having a front surface and a back surface;   exposing a backside of at least one plate of the capacitor; and   electrically connecting the backside of the capacitor plate to the frontside of integrated circuit chip using one or more vias which extend through the encapsulation layer at a location between the integrated circuit chip and the passive component.   
     
     
         16 . The method of  claim 15 , wherein electrically connecting comprises:
 forming a first conductive track on the front surface between the integrated circuit chip and the via; and   forming a second conductive track on the back surface between the via and the backside of the at least one plate of the capacitor.   
     
     
         17 . The method of  claim 16 , further comprising forming an additional via between the second conductive track and the backside of the at least one plate of the capacitor. 
     
     
         18 . The method of  claim 15 , further comprising singulating the device from a wafer-scale production of multiple same devices. 
     
     
         19 . The method of  claim 15 , wherein the capacitor is oriented with the plate parallel to the front and back surfaces. 
     
     
         20 . The method of  claim 15 , wherein the capacitor is oriented with the plate perpendicular to the front and back surfaces.