Electrostatic discharge protection device

Abstract

The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region. The first metal contact and a second metal contact are separated by a poly pattern or an insulating layer pattern disposed on the first well region.

What is claimed is: 
     
         1 . An electrostatic discharge (ESD) protection device, comprising:
 a semiconductor substrate having an active region;   a first well region having a first conductive type formed in the active region;   a first doped region having the first conductive type formed in the first well region;   a first metal contact disposed on the first doped region; and   a second metal contact disposed on the active region, connecting to the first well region, wherein the first metal contact and a second metal contact are separated by a poly pattern disposed on the first well region.   
     
     
         2 . The ESD protection device as claimed in  claim 1 , further comprising:
 a first silicide pattern and a second silicide pattern respectively covering portions of the first well region, wherein the first silicide pattern is disposed between the first metal contact and the first doped region, and the second silicide pattern is disposed between the second metal contact and the first well region.   
     
     
         3 . The ESD protection device as claimed in  claim 2 , wherein the first silicide pattern and the second silicide pattern are respectively adjacent to two opposite sides of the poly pattern. 
     
     
         4 . The ESD protection device as claimed in  claim 1 , further comprising:
 a second doped region having the first conductive type formed in the first well region, wherein the second metal contact is disposed on the second doped region.   
     
     
         5 . The ESD protection device as claimed in  claim 4 , wherein a dopant concentration of the second doped region is less than that of the first doped region. 
     
     
         6 . The ESD protection device as claimed in  claim 1 , wherein a dopant concentration of the first doped region is larger than that of the first well region. 
     
     
         7 . The ESD protection device as claimed in  claim 1 , further comprising:
 a second well region having a second conductive type opposite to the first conductive type formed in the active region surrounding a boundary of the first well region;   a third doped region having the second conductive type formed in the second well region, wherein a dopant concentration of the third doped region is larger than that of the second well region; and   a third metal contact disposed on the third doped region.   
     
     
         8 . The ESD protection device as claimed in  claim 7 , wherein the third doped region and the second doped region are separated by an isolation pattern. 
     
     
         9 . The ESD protection device as claimed in  claim 7 , further comprising a third well region formed in the active region, contacting bottoms of the first and second well regions when the semiconductor substrate has the first conductive type. 
     
     
         10 . The ESD protection device as claimed in  claim 7 , wherein the semiconductor substrate has the second conductive type. 
     
     
         11 . The ESD protection device as claimed in  claim 7 , wherein a dopant concentration of the second doped region is larger than that of the second well region. 
     
     
         12 . The ESD protection device as claimed in  claim 1 , further comprising:
 a second well region having the first conductive type formed in the active region surrounding a boundary of the first well region.   
     
     
         13 . The ESD protection device as claimed in  claim 1 , wherein the first conductive type is n-type and the semiconductor substrate is p-type, and the first metal contact is coupled to an input/output device and the second metal contact is coupled to a high voltage power supply terminal or the first metal contact is coupled to a low voltage power supply terminal and the second metal contact is coupled to an input/output device. 
     
     
         14 . The ESD protection device as claimed in  claim 1 , wherein the first conductive type is p-type and the semiconductor substrate is p-type, and the first metal contact is coupled to a high voltage power supply terminal and the second metal contact is coupled to an input/output device or the first metal contact is coupled to an input/output device and the second metal contact is coupled to a low voltage power supply terminal. 
     
     
         15 . The ESD protection device as claimed in  claim 1 , further comprising spacers disposed on two opposite sidewalls of the poly pattern, respectively. 
     
     
         16 . The ESD protection device as claimed in  claim 1 , wherein the poly pattern or the insulating layer pattern is electrically floating. 
     
     
         17 . The ESD protection device as claimed in  claim 1 , wherein the second metal contact and the first well region are formed as a Schottky diode. 
     
     
         18 . An electrostatic discharge (ESD) protection device, comprising:
 a semiconductor substrate having an active region;   a first well region having a first conductive type formed in the active region;   a first doped region having the first conductive type formed in the first well region;   a first metal contact disposed on the first doped region; and   a second metal contact disposed on the active region, connecting to the first well region, wherein at least a portion of an upper surface of the first well region does not have silicide.   
     
     
         19 . An electrostatic discharge (ESD) protection device, comprising:
 a semiconductor substrate having an active region;   a first well region having a first conductive type formed in the active region;   a first doped region having the first conductive type formed in the first well region;   a first metal contact disposed on the first doped region; and   a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.