Ferroelectric random access memory with optimized hardmask

Abstract

Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer on an upper surface of the second electrode. The second electrode may be comprised of a second conductor, and the cap layer may have a composition that is free of titanium. The second electrode may be formed by etching a layer of a material formed on a layer of the second conductor to define a hardmask and then modifying the remaining portion of that material in the hardmask to have a comparatively less etch rate, when exposed to a chlorine-based reactive ion etch chemistry, than when initially formed.

What is claimed is: 
     
         1 . A device structure comprising:
 a first electrode comprised of a first conductor;   a ferroelectric layer on the first electrode;   a second electrode on the ferroelectric layer, the second electrode comprised of a second conductor and having an upper surface; and   a cap layer on the upper surface of the second electrode,   wherein the cap layer has a composition that is free of titanium.   
     
     
         2 . The device structure of  claim 1  wherein the first conductor is comprised of a platinum group metal or a metal oxide containing a platinum group metal. 
     
     
         3 . The device structure of  claim 2  wherein the second conductor is comprised of a platinum group metal or a metal oxide containing a platinum group metal. 
     
     
         4 . The device structure of  claim 1  wherein the first conductor is comprised of iridium oxide. 
     
     
         5 . The device structure of  claim 1  wherein the cap layer is comprised of aluminum oxide. 
     
     
         6 . The device structure of  claim 1  wherein the cap layer is in direct contact with the upper surface of the second electrode. 
     
     
         7 . The device structure of  claim 1  wherein the cap layer includes sidewalls that are free of rail layers of the second conductor originating from patterning of the second electrode, and the cap layer is free of blisters. 
     
     
         8 . The device structure of  claim 1  wherein the first electrode, the second electrode, and the ferroelectric layer separating the first electrode from the second electrode comprise a capacitor structure for memory cell of a ferroelectric memory (FRAM). 
     
     
         9 . The device structure of  claim 8  further comprising:
 a transistor having a drain and a source coupled with the second electrode. 
 
     
     
         10 . The device structure of  claim 9  wherein the second electrode is segmented into a plurality of sections, and further comprising:
 an insulator layer on which the first electrode is formed; 
 a dielectric layer covering the capacitor structure; 
 a plurality of wires in the dielectric layer; and 
 via plugs in the dielectric layer, the via plugs coupling the wires with the plurality of sections of the second electrode, 
 wherein the wires are further coupled with the source of the transistor. 
 
     
     
         11 . The device structure of  claim 1  wherein the cap layer has an upper surface, and further comprising:
 an encapsulation layer on the upper surface of the cap layer, the encapsulation layer separated from the upper surface of the second electrode by the cap layer. 
 
     
     
         12 . A design structure readable by a machine used in design, manufacture, or simulation of an integrated circuit, the design structure comprising:
 a first electrode comprised of a first conductor;   a ferroelectric layer on the first electrode;   a second electrode on the ferroelectric layer, the second electrode comprised of a second conductor and having an upper surface; and   a cap layer on the upper surface of the second electrode,   wherein the cap layer has a composition that is free of titanium.   
     
     
         13 . The design structure of  claim 12  wherein the design structure comprises a netlist. 
     
     
         14 . The design structure of  claim 12  wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. 
     
     
         15 . The design structure of  claim 12  wherein the design structure resides in a programmable gate array.