ADHESION LAYER AND MULTIPHASE ULTRA-LOW k DIELECTRIC MATERIAL

Abstract

A dielectric material incorporating a graded carbon adhesion layer whereby the content of C increases with layer thickness and a multiphase ultra low k dielectric comprising a porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is described. A semiconductor integrated circuit incorporating the above dielectric material in interconnect wiring is described and a semiconductor integrated circuit incorporating the above multiphase ultra low k dielectric in a gate stack spacer of a FET is described.

1 - 25 . (canceled) 
     
     
         26 . A dielectric material having a first graded dielectric layer of silicon oxide and organo-silicon where a content of C increases with thickness and a second porous SiCOH layer having a tri-dimensional random covalently bond network of Si—O, Si—C, Si—CH 2 —Si, C—O, Si—H, and C—H bonds, said second porous SiCOH layer having a dielectric constant k lower than 2.7 and a modulus of elasticity greater than 7 GPa. 
     
     
         27 . The dielectric material of  claim 26  wherein said content C in said first graded dielectric layer increases with thickness to above 30 percent. 
     
     
         28 . The dielectric material of  claim 26  wherein said content C in said first graded dielectric layer increases with thickness from 0 percent to above 30 percent. 
     
     
         29 . The dielectric material of  claim 26  wherein said first graded dielectric layer thickness is in the range from 3 nm to 7 nm. 
     
     
         30 . The dielectric material of  claim 26  wherein said first graded dielectric layer is formed on a substrate, said substrate selected from the group consisting of a semiconductor, an insulator, a metal and combinations thereof. 
     
     
         31 . The dielectric material of  claim 26  wherein said second porous SiCOH dielectric layer has a dielectric constant k lower than 2.5 and a modulus of elasticity greater than 6 GPa. 
     
     
         32 . The dielectric material of  claim 26  wherein said second porous SiCOH dielectric layer has a porosity greater than 13.8 percent. 
     
     
         33 . The dielectric material of  claim 26  further comprising Si—(CH 2 ) n —Si bonds. 
     
     
         34 . A semiconductor integrated circuit comprising an interconnect wiring having a dielectric material having a first graded dielectric layer of silicon oxide and organo-silicon where a content of C increases with thickness and a second porous SiCOH layer having a tri-dimensional random covalently bond network having a dielectric constant k lower than 2.7 and a modulus of elasticity greater than 7 GPa. 
     
     
         35 . The semiconductor integrated circuit of  claim 34  wherein said content C in said first graded dielectric layer increases with thickness to above 30 percent. 
     
     
         36 . The semiconductor integrated circuit of  claim 34  wherein said content C in said first graded dielectric layer increases with thickness from 0 percent to above 30 percent. 
     
     
         37 . The semiconductor integrated circuit of  claim 34  wherein said first graded dielectric layer thickness is in the range from 3 nm to 7 nm. 
     
     
         38 . The semiconductor integrated circuit of  claim 34  wherein said first graded dielectric layer is formed on a substrate, said substrate selected from the group consisting of a semiconductor, an insulator, a metal and combinations thereof. 
     
     
         39 . The semiconductor integrated circuit of  claim 34  wherein said second porous SiCOH dielectric layer has a dielectric constant k lower than 2.5 and a modulus of elasticity greater than 6 GPa. 
     
     
         40 . The semiconductor integrated circuit of  claim 34  wherein said second porous SiCOH dielectric layer has a porosity greater than 13.8 percent. 
     
     
         41 . A semiconductor integrated circuit comprising a FET having a gate stack spacer including a first porous SiCOH dielectric material having a tri-dimensional random covalently bond network having a dielectric constant k lower than 2.7 and a modulus of elasticity greater than 7 GPa. 
     
     
         42 . The semiconductor integrated circuit of  claim 41  wherein said first porous SiCOH dielectric material has a dielectric constant k lower than 2.5 and a modulus of elasticity greater than 6 GPa. 
     
     
         43 . The semiconductor integrated circuit of  claim 41  further including a second dielectric material having a first graded dielectric layer of silicon oxide and organo-silicon where a content of C increases with thickness. 
     
     
         44 . The semiconductor integrated circuit of  claim 41  wherein said second dielectric material is positioned between a third material and said first material to provide adhesion.