Switchable memory diodes based on ferroelectric/conuugated polymer heterostructures and/or their composites

Abstract

An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array.

1 - 20 . (canceled) 
     
     
         21 . A memory cell comprising:
 a layer comprising a composite of a first material and a second material, the second material being ferroelectric material.   
     
     
         22 . The memory cell of  claim 21  wherein the first material is a conjugated polymer. 
     
     
         23 . The memory cell of  claim 22  and further comprising first and second electrodes, the layer being between the first and second electrodes. 
     
     
         24 . The memory cell of  claim 23  and further comprising a zener diode in series with the memory cell. 
     
     
         25 . A memory array comprising:
 a plurality of bit lines;   a plurality of word lines orthogonal to the bit lines and forming intersections therewith; and   a plurality of memory structures each connecting a bit line with a word line at an intersection thereof, each memory structure comprising a memory cell comprising a first layer, and a second layer comprising ferroelectric material.   
     
     
         26 . The memory array of  claim 25  wherein the first layer comprises a conjugated polymer. 
     
     
         27 . The memory array of  claim 25  wherein the first layer comprises semiconductor material. 
     
     
         28 . The memory array of  claim 25  wherein the first layer comprises ferroelectric material. 
     
     
         29 . The memory array of  claim 26  wherein the first and second layers form a pn junction. 
     
     
         30 . The memory array of  claim 27  wherein the first and second layers form a pn junction. 
     
     
         31 . The memory array of  claim 26  wherein each memory structure further comprises a zener diode in series with the memory cell. 
     
     
         32 . The memory array of  claim 27  wherein each memory structure further comprises a zener diode in series with the memory cell. 
     
     
         33 . The memory array of  claim 28  wherein each memory structure further comprises a zener diode in series with the memory cell. 
     
     
         34 . A memory array comprising:
 a plurality of bit lines;   a plurality of word lines orthogonal to the bit lines and forming intersections therewith; and   a plurality of memory structures each connecting a bit line with a word line at an intersection thereof, each memory structure comprising a memory cell comprising a composite of first and second materials, one of the materials being ferroelectric material.   
     
     
         35 . The memory array of  claim 34  wherein the other material comprises a conjugated polymer. 
     
     
         36 . The memory array of  claim 35  wherein each memory structure further comprises a zener diode in series with the memory cell.