Interconnected ring network in a multi-processor system

Abstract

In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

1 . A system comprising:
 a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores;   a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores;   a first global interface module configured to form an interface between the first ring network and a third ring network by transmitting data between the first ring network and the third ring network, the third ring network interconnecting the first ring network and the second ring network; and   a second global interface module configured to form an interface between the second ring network and the third ring network by transmitting data between the second ring network and the third ring network.   
     
     
         2 . The system of  claim 1 , further comprising:
 a plurality of caches, ones of the first and second plurality of processing cores being coupled to a respective cache of the plurality of caches.   
     
     
         3 . The system of  claim 2 , wherein a first cache of the plurality of caches is coupled to a first processor of the first plurality of processors, the first cache being configured to be accessed by the first processor by bypassing the first and the second ring networks. 
     
     
         4 . The system of  claim 3 , wherein the first cache is configured to be accessed, via the first ring network, by a second processor of the first plurality of processors. 
     
     
         5 . The system of  claim 4 , wherein the first cache is configured to be accessed, via (i) the second ring network, (ii) the third ring network, and (iii) the first ring network, by a third processor of the second plurality of processors. 
     
     
         6 . The system of  claim 2 , wherein ones of the plurality of caches are included in or coupled to a corresponding one of the first and second plurality of core interface modules. 
     
     
         7 . The system of  claim 2 , wherein:
 a first processor of the first plurality of processors is coupled to a first cache of the plurality of caches;   a second processor of the first plurality of processors is coupled to a second cache of the plurality of caches;   a third processor of the second plurality of processors is coupled to a third cache of the plurality of caches; and   the first processor is configured to (i) access, by bypassing the first and second ring networks, the first cache to read first data from the first cache, (ii) access, via the first ring network, the second cache to read second data from the second cache, and (iii) access, via the first, second and third ring networks, the third cache to read third data from the third cache.   
     
     
         8 . The system of  claim 2 , wherein:
 a first processor of the first plurality of processors is coupled to a first cache of the plurality of caches;   a second processor of the first plurality of processors is coupled to a second cache of the plurality of caches;   a third processor of the second plurality of processors is coupled to a third cache of the plurality of caches; and   the first processor is configured to (i) access the first cache to read first data from the first cache, (ii) in response to the first data not being cached in the first cache, access the second cache to read the first data from the second cache, and (iii) in response to the first data not being cached in the first and second caches, access the third cache to read the first data from the third cache.   
     
     
         9 . The system of  claim 8 , wherein:
 the first processor is further configured to, in response to the first data not being cached in the first, second and third caches, access a memory coupled to one of the first and second ring networks to read the first data from the memory.   
     
     
         10 . The system of  claim 1 , further comprising:
 a third plurality of processing cores, ones of the third plurality of processing cores coupled to a respective core interface module among a third plurality of core interface modules, the third plurality of core interface modules configured to be coupled to form in a fourth ring network of processing cores; and   a third global interface module configured to form an interface between the third ring network and the fourth ring network.   
     
     
         11 . A method comprising:
 communicating, by ones of a first plurality of processing cores coupled to a respective one of a first plurality of core interface modules, with the respective core interface module of the first plurality of core interface modules, the first plurality of core interface modules being arranged in a first ring network;   communicating, by ones of a second plurality of processing cores coupled to a respective ones of a second plurality of core interface modules, with the respective core interface module of the second plurality of core interface modules, the second plurality of core interface modules arranged in a second ring network;   interfacing, by a first global interface module, between the first ring network and a third ring network by transmitting data between the first ring network and the third ring network, the third ring network interconnecting the first ring network and the second ring network; and   interfacing, by a second global interface module, between the second ring network and a third ring network by transmitting data between the second ring network and the third ring network.   
     
     
         12 . The method of  claim 10 , wherein ones of the first and second plurality of processing cores is coupled to a respective cache of a plurality of caches, the method further comprising:
 communicating, by ones of the plurality of caches, with one or more of the first and second plurality of processing cores.   
     
     
         13 . The method of  claim 12 , wherein a first cache of the plurality of caches is coupled to a first processor of the first plurality of processors, the method further comprising:
 accessing, by the first processor by bypassing the first and the second ring network, the first cache.   
     
     
         14 . The method of  claim 13 , further comprising:
 accessing, by a second processor of the first plurality of processors, the first cache via the first ring network.   
     
     
         15 . The method of  claim 14 , further comprising:
 accessing, by a third processor of the second plurality of processors, the first cache via (i) the second ring network, (ii) the third ring network, and (iii) the first ring network.   
     
     
         16 . The method of  claim 12 , further comprising:
 coupling ones of the plurality of caches to a corresponding one of the first and second plurality of core interface modules.   
     
     
         17 . The method of  claim 12 , a first processor of the first plurality of processors being coupled to a first cache of the plurality of caches, a second processor of the first plurality of processors being coupled to a second cache of the plurality of caches, a third processor of the second plurality of processors being coupled to a third cache of the plurality of caches, the method further comprising:
 accessing, by the first processor by bypassing the first and second ring networks, the first cache to read first data from the first cache;   accessing, by the first processor via the first ring network, the second cache to read second data from the second cache; and   accessing, by the first processor via the first, second and third ring networks, the third cache to read third data from the third cache.   
     
     
         18 . The method of  claim 12 , a first processor of the first plurality of processors being coupled to a first cache of the plurality of caches, a second processor of the first plurality of processors being coupled to a second cache of the plurality of caches, a third processor of the second plurality of processors being coupled to a third cache of the plurality of caches, the method further comprising:
 accessing, by the first processor, the first cache to read first data from the first cache;   in response to the first data not being cached in the first cache, accessing, by the first processor, the second cache to read the first data from the second cache; and   in response to the first data not being cached in the first and second caches, accessing, by the first processor, the third cache to read the first data from the third cache.   
     
     
         19 . The method of  claim 18 , wherein:
 in response to the first data not being cached in the first, second and third caches, accessing, by the first processor, a memory coupled to one of the first and second ring networks to read the first data from the memory.   
     
     
         20 . The method of  claim 10 , further comprising:
 communicating, by ones of a third plurality of processing cores coupled to a respective ones of a third plurality of core interface modules, with the respective core interface module of the third plurality of core interface modules, the third plurality of core interface modules arranged in a fourth ring network; and   interfacing, by a third global interface module, between the fourth ring network and the third ring network.   
     
     
         21 .- 103 . (canceled)