Chip arrangement and a method for manufacturing a chip arrangement

Abstract

A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

What is claimed is: 
     
         1 . A chip arrangement, comprising:
 a carrier;   a first chip electrically connected to the carrier;   a ceramic layer disposed over the carrier; and   a second chip disposed over the ceramic layer;   wherein the ceramic layer has a porosity in the range from 3% to 70%.   
     
     
         2 . The chip arrangement according to  claim 1 ,
 wherein the first chip comprises a power semiconductor chip.   
     
     
         3 . The chip arrangement according to  claim 2 ,
 wherein the power semiconductor chip comprises at least one power semiconductor device from the group consisting of: a power transistor, a power MOS transistor, a power bipolar transistor, a power field effect transistor, a power insulated gate bipolar transistor, a thyristor, a MOS controlled thyristors, a silicon controlled rectifier, a power schottky diode, a silicon carbide diode, a gallium nitride device.   
     
     
         4 . The chip arrangement according to  claim 1 ,
 wherein the second chip comprises a semiconductor logic chip or a semiconductor memory chip.   
     
     
         5 . The chip arrangement according to  claim 4 ,
 wherein the semiconductor logic chip comprises a semiconductor logic device from the group consisting of: an application specific integrated circuit, a driver, a controller, and a sensor.   
     
     
         6 . The chip arrangement according to  claim 1 ,
 wherein a first chip side is electrically connected to the carrier via an electrically conductive medium.   
     
     
         7 . The chip arrangement according to  claim 6 ,
 wherein the electrically conductive medium comprises at least one from the following group of materials, the group consisting of: a solder, a soft solder, a diffusion solder, a paste, a nanopaste, an adhesive, an electrically conductive adhesive and a thermally conductive adhesive.   
     
     
         8 . The chip arrangement according to  claim 1 ,
 wherein the ceramic layer is adhered directly on the carrier by means of an adhesive material.   
     
     
         9 . The chip arrangement according to  claim 1 ,
 wherein the ceramic layer comprises at least one of an electrically insulating material and a thermally conducting material.   
     
     
         10 . The chip arrangement according to  claim 1 ,
 wherein the ceramic layer comprises one or more particles, the one or more particles comprising at least one from the following group of materials, the group of materials consisting of: aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, silicon carbide, titanium dioxide, titanium nitride, zirconium dioxide, boron nitride, boron carbide.   
     
     
         11 . The chip arrangement according to  claim 10 ,
 wherein the ceramic layer further comprises a filler material, the filler material comprising at least one from the following group of materials, the group of materials consisting of: an organic material, plastic, epoxy, polyimide, thermoset, polyacrylate, silicone and silica.   
     
     
         12 . The chip arrangement according to  claim 1 ,
 wherein the carrier comprises an electrically conductive material.   
     
     
         13 . The chip arrangement according to  claim 1 ,
 wherein the carrier comprises a lead frame, the lead frame comprising at least one from the following group of materials, the group of materials consisting of: copper, nickel, iron, silver, gold, palladium, phosphorous, copper alloy, nickel alloy, iron alloy, silver alloy, gold alloy, palladium alloy, phosphorous alloy.   
     
     
         14 . The chip arrangement according to  claim 1 , further comprising
 an encapsulation material disposed over the carrier, wherein the encapsulation material at least partially surrounds the first chip and the second chip, and one or more lateral sides of the carrier.   
     
     
         15 . The chip arrangement according to  claim 1 , further comprising
 at least one electrically conductive layer formed at least one of over and under the ceramic layer.   
     
     
         16 . The chip arrangement according to  claim 1 ,
 wherein the at least one electrically conductive layer comprises at least one from the following group of materials, the group of materials consisting of: tin, lead, silver, copper, nickel, palladium, zinc, aluminum, gold, antimony, inorganic elements and organic elements.   
     
     
         17 . A method for manufacturing a chip arrangement, the method comprising:
 electrically connecting a first chip to a carrier;   disposing a ceramic layer having a porosity in the range from 3% to 70% over the carrier; and   disposing a second chip over the ceramic layer.   
     
     
         18 . The method according to  claim 17 , comprising
 adhering the ceramic layer directly on the carrier by means of an adhesive material.   
     
     
         19 . The method according to  claim 17 ,
 wherein the ceramic layer comprises at least one of an electrically insulating material and a thermally conducting material.   
     
     
         20 . The method according to  claim 17 ,
 wherein the ceramic layer comprises one or more particles, the one or more particles comprising at least one from the following group of materials, the group of materials consisting of: aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, silicon carbide, titanium dioxide, titanium nitride, zirconium dioxide, boron nitride, boron carbide.   
     
     
         21 . The method according to  claim 17 ,
 wherein the carrier comprises a lead frame, the lead frame comprising at least one from the following group of materials, the group of materials consisting of: copper, nickel, iron, silver, gold, palladium, phosphorous, copper alloy, nickel alloy, iron alloy, silver alloy, gold alloy, palladium alloy, phosphorous alloy.   
     
     
         22 . The method according to  claim 17 , further comprising
 disposing an encapsulation material over the carrier, wherein the encapsulation material at least partially surrounds the first chip and the second chip, and one or more lateral sides of the carrier.   
     
     
         23 . The method according to  claim 17 , further comprising
 forming at least one electrically conductive layer over the carrier before depositing the ceramic layer; and   depositing the ceramic layer over the at least one electrically conductive layer.   
     
     
         24 . The method according to  claim 17 , further comprising
 forming at least one electrically conductive layer over the ceramic layer;   and forming the second chip over the least one electrically conductive layer.   
     
     
         25 . The method according to  claim 17 , comprising
 electrically connecting the first chip to the carrier via an electrically conductive medium comprising at least one material from the following group of materials, the group consisting of: a solder, a soft solder, a diffusion solder, a paste, a nanopaste, an adhesive, an electrically conductive adhesive, a thermally conductive adhesive.   
     
     
         26 . The method according to  claim 17 ,
 wherein the first chip comprises a power semiconductor chip.   
     
     
         27 . The method according to  claim 17 ,
 wherein the second chip comprises a semiconductor logic chip or a semiconductor memory chip.