Package substrate and semiconductor package including the same

Abstract

A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.

What is claimed is: 
     
         1 . A package substrate comprising:
 an insulating substrate having an upper surface on which a semiconductor chip is arranged via a signal bump and a dummy bump, the signal bump and the dummy bump having substantially the same thickness;   a dummy pad having an upper surface, the dummy pad on the upper surface of the insulating substrate and connected to the dummy bump;   a signal pad formed on the upper surface of the insulating substrate and connected to the signal bump, the signal pad having a protrusion that has an upper surface higher than the upper surface of the dummy pad; and   a plug having an upper end and a lower end, the upper end exposed through the upper surface of the insulating substrate and electrically connected with the signal pad and the dummy pad, and the lower end exposed through a lower surface of the insulating substrate.