Apparatus including memory system controllers and related methods

Abstract

Memory system controllers can include a host bus adapter (HBA) and a serial advanced technology attachment (SA) programming compliant device coupled to the HBA via a function-specific interconnect configured to simultaneously transfer a command, a response, and other information between the HBA and the SA programming compliant device.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a host bus adapter (HBA); and   a serial attachment (SA) programming compliant device coupled to the HBA via a function-specific interconnect configured to simultaneously transfer a command, a response, and other information between the HBA and the SA programming compliant device.   
     
     
         2 . The apparatus of  claim 1 , wherein the function-specific interconnect includes:
 a command output on the HBA coupled to a command input on the SA programming compliant device;   a response output on the SA programming compliant device coupled to a response input on the HBA;   a write information output on the HBA coupled to a write information input on the SA programming compliant device; and   a read information output on the SA programming compliant device coupled to a read information input on the HBA.   
     
     
         3 . The apparatus of  claim 2 , wherein the command, response, write information, and read information input/output pairs are unidirectional and employ neither 8b10b encoding nor primitives. 
     
     
         4 . The apparatus of  claim 1 , wherein the function-specific interconnect is configured to operate a command interface, a response interface, and an information interface concurrently in response to a first command protocol. 
     
     
         5 . The apparatus of  claim 4 , wherein the function-specific interconnect is configured to operate the command interface, the response interface, and the information interfaces atomically in response to a second command protocol. 
     
     
         6 . The apparatus of  claim 1 , wherein the HBA includes:
 a command fetcher;   a response receiver;   a downstream direct memory access (DMA) device; and   an upstream DMA device.   
     
     
         7 . The apparatus of  claim 6 , wherein the SA programming compliant device includes:
 a device-to-host (DH) arbiter;   a command finite state machine (FSM) coupled to the DH arbiter;   a write FSM coupled to the DH arbiter; and   a read FSM coupled to the DH arbiter;   wherein the DH arbiter is configured to qualify an order of information delivery and communicate completions to the HBA based on input from the command FSM, the write FSM, and the read FSM.   
     
     
         8 . The apparatus of  claim 7 , wherein the write FSM includes a write buffer configured to buffer write information before the DH arbiter qualifies the order of write information delivery. 
     
     
         9 . The apparatus of  claim 7 , wherein the read FSM includes a read buffer configured to buffer read information before the DH arbiter qualifies the order of read information delivery. 
     
     
         10 . The apparatus of  claim 1 , wherein the SA programming compliant device comprises a serial advanced technology attachment (SATA) programming compliant device. 
     
     
         11 . The apparatus of  claim 1 , wherein the SA programming compliant device comprises a serial attached small computer system interface (SAS) programming compliant device. 
     
     
         12 . A method, comprising:
 transferring a command between a host bus adapter (HBA) and a serial attachment (SA) programming compliant device;   transferring a response between the HBA and the SA programming compliant device simultaneously with the command; and   transferring other information between the HBA and the SA programming compliant device simultaneously with the command.   
     
     
         13 . The method of  claim 12 , wherein the method includes:
 transferring the command via a command interface between the HBA and the SA programming compliant device;   transferring the response via a response interface between the HBA and the SA programming compliant device; and   transferring the other information via an information interface between the HBA and the SA programming compliant device.   
     
     
         14 . The method of  claim 13 , wherein the method includes operating the command interface, the response interface, and the information interface concurrently in response to a first command protocol. 
     
     
         15 . The method of  claim 13 , wherein the method includes operating the command interface, the response interface, and the information interface atomically in response to a second command protocol. 
     
     
         16 . The method of  claim 12 , wherein the method includes qualifying an order of information delivery and communicating completions to the HBA based on input from a command finite state machine, a write finite state machine, and a read finite state machine. 
     
     
         17 . The method of  claim 16 , wherein the method includes:
 buffering read information before qualifying the order of read information delivery; and   buffering write information before qualifying the order of write information delivery.   
     
     
         18 . An apparatus, comprising:
 a host bus adapter (HBA), including:
 a command output; 
 a response input; 
 a write information output; and 
 a read information input; and 
   a serial attachment (SA) programming compliant device, including:
 a command input coupled to the command output; 
 a response output coupled to the response input; 
 a write information input coupled to the write information output; and 
 a read information output coupled to the read information input. 
   
     
     
         19 . The apparatus of  claim 18 , wherein the HBA includes a plurality of direct memory access (DMA) devices configured to provide concurrent delivery of a command, receipt of a response, delivery of write information, and receipt of read information. 
     
     
         20 . The apparatus of  claim 18 , wherein the SA programming compliant device includes a plurality of finite state machines (FSMs) configured to provide concurrent receipt of a command, delivery of a response, receipt of write information, and delivery of read information.