Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor

Abstract

A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

1 . A semiconductor layer stack comprising:
 a first electrode layer formed above a substrate;   a first metal oxide formed on the first electrode layer,
 wherein the first metal oxide has a thickness of less than between 1 A and 15 A, 
 wherein the first metal oxide is less than 30% crystalline, and 
 wherein the first metal oxide has a resistivity greater than 0.01 ohm-cm; 
   a dielectric layer formed above the first metal oxide,
 wherein the dielectric layer is crystalline; 
   a second metal oxide formed on the dielectric layer,
 wherein the second metal oxide has a thickness between 1 A and 15 A, 
 wherein the second metal oxide is less than 30% crystalline, and 
 wherein the second metal oxide has a resistivity greater than 0.01 ohm-cm; and 
   a second electrode layer formed above the second metal oxide.   
     
     
         2 . The semiconductor layer stack of  claim 1 , wherein the first electrode layer comprises one of ruthenium, platinum, titanium nitride, tantalum nitride, titanium aluminum-nitride, tungsten, tungsten nitride, molybdenum, molybdenum nitride, or vanadium nitride. 
     
     
         3 . The semiconductor layer stack of  claim 1 , wherein the first metal oxide comprises one of molybdenum oxide, tungsten oxide, ruthenium oxide, iridium oxide, chromium oxide, manganese oxide, cerium oxide, europium oxide, or tin oxide. 
     
     
         4 . The semiconductor layer stack of  claim 3 , wherein the first metal oxide comprises molybdenum oxide. 
     
     
         5 . The semiconductor layer stack of  claim 1 , wherein the dielectric layer comprises one of aluminum oxide, barium-strontium-titanate (BST), hafnium oxide, hafnium silicate, niobium oxide, lead-zirconium-titanate (PZT), a bilayer of silicon oxide and silicon nitride, silicon oxy-nitride, strontium-titanate (STO), tantalum oxide, titanium oxide, zirconium oxide or doped versions of the same. 
     
     
         6 . The semiconductor layer stack of  claim 5 , wherein the dielectric layer comprises zirconium oxide or a doped version of the same. 
     
     
         7 . The semiconductor layer stack of  claim 6 , wherein the dielectric layer further comprises a dopant comprising at least one of Al, Ce, Co, Er, Ga, Gd, Ge, Hf, In, La, Lu, Mg, Mn, Nd, Pr, Sc, Si, Sn, Sr, Y, or Zr. 
     
     
         8 - 12 . (canceled) 
     
     
         13 . The semiconductor layer stack of  claim 1 , wherein the second electrode layer comprises one of ruthenium, platinum, titanium nitride, tantalum nitride, titanium aluminum-nitride, tungsten, tungsten nitride, molybdenum, molybdenum nitride, or vanadium nitride. 
     
     
         14 . The semiconductor layer stack of  claim 13 , wherein the second electrode layer comprises titanium nitride. 
     
     
         15 . The semiconductor layer stack of  claim 1 , wherein the second metal oxide comprises one of molybdenum oxide, tungsten oxide, ruthenium oxide, iridium oxide, chromium oxide, manganese oxide, cerium oxide, europium oxide, or tin oxide. 
     
     
         16 . The semiconductor layer stack of  claim 15 , wherein the second metal oxide comprises molybdenum oxide. 
     
     
         17 . The semiconductor layer stack of  claim 15 , wherein the second metal oxide comprises cerium oxide. 
     
     
         18 - 19 . (canceled) 
     
     
         20 . The semiconductor layer stack of  claim 1 , wherein the dielectric layer comprises zirconium oxide doped with aluminum. 
     
     
         21 . The semiconductor layer stack of  claim 20 , wherein a concentration of aluminum in the dielectric layer is about 20 atomic %. 
     
     
         22 . The semiconductor layer stack of  claim 1 , wherein the second metal oxide comprises europium oxide. 
     
     
         23 . The semiconductor layer stack of  claim 1 , wherein the dielectric layer comprises titanium oxide in a rutile phase. 
     
     
         24 . The semiconductor layer stack of  claim 1 , wherein the dielectric layer has a thickness of between about 50 A and 80 A. 
     
     
         25 . The semiconductor layer stack of  claim 1 , wherein a thickness of the dielectric layer is greater than the thickness of the first metal oxide. 
     
     
         26 . The semiconductor layer stack of  claim 1 , wherein the dielectric layer has a nanolaminate structure. 
     
     
         27 . The semiconductor layer stack of  claim 1 , wherein the first metal oxide has a work function of at least about 5.0 eV.