Nonvolatile memory apparatus

Abstract

A nonvolatile memory apparatus includes a sensing voltage generation unit, a memory cell, a current copy unit and a data sensing unit. The sensing voltage generation unit provides a sensing voltage with a constant level, to a sensing node. The memory cell receives the sensing voltage from the sensing node. The current copy unit generates copied current with substantially the same magnitude as sensing current which flows through the memory cell. The data sensing unit senses the copied current and generates a multi-bit data output signal.

What is claimed is: 
     
         1 . A nonvolatile memory apparatus comprising:
 a sensing voltage generation unit configured to provide a sensing voltage with a constant level, to a sensing node;   a memory cell configured to receive the sensing voltage from the sensing node;   a current copy unit configured to generate copied current with substantially the same magnitude as sensing current which flows through the memory cell; and   a data sensing unit configured to sense the copied current and generate a multi-bit data output signal.   
     
     
         2 . The nonvolatile memory apparatus according to  claim 1 , wherein the sensing voltage generation unit comprises:
 a comparator configured to compare a reference voltage and a voltage level of the sensing node and generate a comparison signal; and   a driver section configured to provide a power supply voltage to the sensing node in response to the comparison signal.   
     
     
         3 . The nonvolatile memory apparatus according to  claim 2 , wherein the driver section comprises a first transistor having a gate which receives the comparison signal, and a drain and a source one of which receives the power supply voltage and the other of which is connected with the sensing node. 
     
     
         4 . The nonvolatile memory apparatus according to  claim 2 , wherein the current copy unit receives the comparison signal and generates the copied current with substantially the same magnitude as the sensing current which flows through the memory cell. 
     
     
         5 . The nonvolatile memory apparatus according to  claim 3 , wherein the current copy unit comprises a second transistor having a gate which receives the comparison signal, and a drain and a source one of which receives the power supply voltage and the other of which generates the copied current. 
     
     
         6 . The nonvolatile memory apparatus according to  claim 1 , wherein the data sensing unit comprises:
 a linear converting section configured to receive the copied current and generate a current amplification signal; and   a digital signal generating section configured to receive the current amplification signal and generate the data output signal.   
     
     
         7 . The nonvolatile memory apparatus according to  claim 6 , wherein the linear converting section comprises a log-to-linear converter which converts the copied current with a log scale into the current amplification signal with a linear scale. 
     
     
         8 . The nonvolatile memory apparatus according to  claim 6 , wherein the digital signal generating section comprises:
 an analog-to-digital converter configured to generate a multi-bit digital signal from the current amplification signal; and   an output part configured to encode the multi-bit digital signal and generate the multi-bit data output signal.   
     
     
         9 . A nonvolatile memory apparatus comprising:
 a sensing voltage generation unit configured to provide a sensing voltage with a constant level, to a sensing node;   a memory cell connected with the sensing node at one end thereof and configured to receive the sensing voltage; and   a data sensing unit connected with the other end of the memory cell and configured to sense sensing current which flows through the memory cell and generate a data output signal.   
     
     
         10 . The nonvolatile memory apparatus according to  claim 9 , wherein the sensing voltage generation unit comprises:
 a comparator configured to compare a reference voltage and a voltage level of the sensing node and generate a comparison signal; and   a driver section configured to provide a power supply voltage to the sensing node in response to the comparison signal and generate the sensing voltage.   
     
     
         11 . The nonvolatile memory apparatus according to  claim 10 , wherein the driver section comprises a MOS transistor having a gate which receives the comparison signal, and a drain and a source one of which receives the power supply voltage and the other of which is connected with the sensing node. 
     
     
         12 . The nonvolatile memory apparatus according to  claim 9 , wherein the data sensing unit compares magnitudes of the sensing current and reference cell current which is generated from a reference cell, and generates the data output signal. 
     
     
         13 . The nonvolatile memory apparatus according to  claim 9 , wherein the data sensing unit receives the sensing current which flows through the memory cell, and generates a multi-bit data output signal. 
     
     
         14 . The nonvolatile memory apparatus according to  claim 13 , wherein the data sensing unit comprises:
 a linear converting section configured to receive the sensing current and generate a current amplification signal; and   a digital signal generating section configured to receive the current amplification signal and generate the multi-bit data output signal.   
     
     
         15 . The nonvolatile memory apparatus according to  claim 14 , wherein the linear converting section comprises a log-to-linear converter which converts the sensing current with a log scale into the current amplification signal with a linear scale. 
     
     
         16 . The nonvolatile memory apparatus according to  claim 14 , wherein the digital signal generating section comprises:
 an analog-to-digital converter configured to generate a multi-bit digital signal from the current amplification signal; and   an output part configured to encode the multi-bit digital signal and generate the multi-bit data output signal.   
     
     
         17 . The nonvolatile memory apparatus according to  claim 9 , further comprising:
 a column switch configured to connect the sensing node and the one end of the memory cell with each other in response to a bit line select signal.   
     
     
         18 . The nonvolatile memory apparatus according to  claim 9 , further comprising:
 a row switch configured to connect the other end of the memory cell with a ground voltage with each other in response to a word line select signal.   
     
     
         19 . The nonvolatile memory apparatus according to  claim 18 , wherein the data sensing unit receives current which flows through the memory cell, between the other end of the memory cell and the word line switch. 
     
     
         20 . The nonvolatile memory apparatus according to  claim 9 , wherein the data sensing unit senses the sensing current and generates the data output signal when activated in response to the word line select signal. 
     
     
         21 . A nonvolatile memory apparatus comprising:
 a memory cell;   a sensing voltage generation unit configured to provide a sensing voltage with a constant level, to a sensing node;   a column switch configured to connect one end of the memory cell with a sensing node in response to a bit line select signal; and   a data sensing unit configured to receive and sense sensing current which flows through the memory cell, from the other end of the memory cell in response to a word line select signal, and generate a data output signal.   
     
     
         22 . The nonvolatile memory apparatus according to  claim 21 , wherein the sensing voltage generation unit comprises:
 a comparator configured to compare a reference voltage and a voltage of the sensing node and generate a comparison signal; and   a driver section configured to provide a power supply voltage to the sensing node in response to the comparison signal.   
     
     
         23 . The nonvolatile memory apparatus according to  claim 22 , wherein the driver section comprises a MOS transistor having a gate which receives the comparison signal, and a drain and a source one of which receives the power supply voltage and the other of which is connected with the sensing node. 
     
     
         24 . The nonvolatile memory apparatus according to  claim 21 , wherein the data sensing unit receives the sensing current when activated in response to the word line select signal, compares current flowing through the memory cell and reference cell current generated from a reference cell, and generate the data output signal. 
     
     
         25 . The nonvolatile memory apparatus according to  claim 21 , wherein the word line select signal is generated on the basis of a row address signal and is enabled for a shorter time than the bit line select signal. 
     
     
         26 . The nonvolatile memory apparatus according to  claim 24 , wherein the word line select signal is directly inputted to the data sensing unit. 
     
     
         27 . A nonvolatile memory apparatus comprising:
 a memory cell array including a plurality of memory cells having one ends which are respectively connected with a plurality of bit lines and other ends which are respectively connected with a plurality of word lines;   a sensing voltage generation block configured to provide a sensing voltage to the memory cell array; and   a data sensing block disposed at a position different from the sensing voltage generation block, and configured to receive and sense sensing current which flows through the memory cells and generate a data output signal.   
     
     
         28 . The nonvolatile memory apparatus according to  claim 27 ,
 wherein the data sensing block includes a plurality of data sensing units which are respectively connected with the plurality of memory cells, and   wherein the plurality of data sensing units compare current which flows through the memory cells respectively connected therewith and reference cell current generated from reference cells, and generate the data output signal.   
     
     
         29 . The nonvolatile memory apparatus according to  claim 28 , wherein the reference cells are disposed in the data sensing block. 
     
     
         30 . A nonvolatile memory apparatus comprising:
 a memory cell array including memory cells one ends of which are respectively connected with a plurality of bit lines;   a sensing voltage generation block configured to provide a sensing voltage to the memory cell array; and   a data sensing block disposed below the memory cell array in a vertical direction, connected with the other ends of the memory cells, and configured to sense current which flows through the memory cells and generate a data output signal.   
     
     
         31 . The nonvolatile memory apparatus according to  claim 30 ,
 wherein the data sensing block includes a plurality of data sensing units which are respectively connected with a plurality of word lines and the plurality of memory cells, and   wherein the plurality of data sensing units respectively receive current flowing through the memory cells when the word lines are enabled, compare the current flowing through the memory cells and reference current generated from reference cells, and generate the data output signal.   
     
     
         32 . The nonvolatile memory apparatus according to  claim 31 , wherein the reference cells are disposed in the memory cell array. 
     
     
         33 . The nonvolatile memory apparatus according to  claim 31 , wherein the reference cells are disposed at a position different from the sensing voltage generation block. 
     
     
         34 . A nonvolatile memory apparatus comprising:
 a sensing voltage generation unit configured to provide a sensing voltage, to a sensing node;   a memory cell configured to receive the sensing voltage from the sensing node;   a current copy unit configured to generate copied current; and   a data sensing unit configured to sense the copied current and generate a data output signal.   
     
     
         35 . The nonvolatile memory apparatus according to  claim 34 , wherein the sensing voltage generation unit provides a sensing voltage with a constant level, to a sensing node. 
     
     
         36 . The nonvolatile memory apparatus according to  claim 34 , wherein the current copy unit generates copied current with substantially the same magnitude as sensing current which flows through the memory cell. 
     
     
         37 . The nonvolatile memory apparatus according to  claim 34 , wherein the data output signal comprises a multi-bit data output signal. 
     
     
         38 . A memory system comprising:
 a memory controller; and   a nonvolatile memory device including a nonvolatile memory apparatus comprising:   a sensing voltage generation unit configured to provide a sensing voltage with a constant level, to a sensing node;   a memory cell configured to receive the sensing voltage from the sensing node;   a current copy unit configured to generate copied current with substantially the same magnitude as sensing current which flows through the memory cell; and   a data sensing unit configured to sense the copied current and generate a data output signal.   
     
     
         39 . An electronic device including a nonvolatile memory apparatus and a central processing unit, the nonvolatile memory apparatus comprising:
 a sensing voltage generation unit configured to provide a sensing voltage with a constant level, to a sensing node;   is a memory cell configured to receive the sensing voltage from the sensing node;   a current copy unit configured to generate copied current with substantially the same magnitude as sensing current which flows through the memory cell; and   a data sensing unit configured to sense the copied current and generate a data output signal.