Electronic system and method for selectively allowing access to a shared memory

Abstract

An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

We claim: 
     
         1 . A computing device method, comprising:
 configuring a main memory bus to pass data at a rate sufficient to operate at least two devices without either of the at least two devices starving for lack of data;   generating first main memory requests with a first processing unit;   passing the first main memory requests to a shared main memory through a first main memory interface and over the main memory bus;   generating second main memory requests with a decoder/encoder;   passing the second main memory requests to the shared main memory through a second main memory interface and over the main memory bus;   receiving the first and second main memory requests from the first processing unit and the decoder/encoder respectively with an arbiter;   arbitrating access to the shared main memory with the arbiter   retrieving software instructions from the shared main memory, the software instructions passed over the main memory bus in real time;   executing the software instructions with the first processing unit;   passing, in real time, video data between the decoder/encoder and the shared main memory over the main memory bus; and   operating the decoder/encoder on the video data.   
     
     
         2 . The computing device method according to  claim 1  wherein configuring the main memory bus to pass data at a rate sufficient to operate at least two devices without either of the at least two devices starving for lack of data includes configuring the main memory bus with a bandwidth at least two times greater than an amount of data carried to the decoder/encoder when the decoder/encoder is operating in real time. 
     
     
         3 . The computing device method according to  claim 2  wherein the main memory bus is configured to carry up to 400 Mbytes/s. 
     
     
         4 . The computing device method according to  claim 1  wherein executing the software instructions with the first processing unit includes directing operations of the decoder/encoder. 
     
     
         5 . The computing device method according to  claim 1 , comprising:
 generating third main memory requests with a refresh logic unit;   passing the third main memory requests to the shared main memory over the main memory bus; and   receiving the third main memory requests from the refresh logic unit with the arbiter.   
     
     
         6 . The computing device method according to  claim 1 , comprising:
 granting, via the arbiter, access to the shared main memory to the decoder/encoder in a first time interval; and   granting, via the arbiter, access to the shared main memory to the first processing unit in a second time interval.   
     
     
         7 . The computing device method according to  claim 6 , comprising:
 determining a priority of access to the shared main memory for the decoder/encoder with a direct memory access (DMA) engine.   
     
     
         8 . The computing device method according to  claim 6 , comprising:
 determining a burst length of access to the shared main memory for the decoder/encoder with a direct memory access (DMA) engine.   
     
     
         9 . The computing device method according to  claim 6 , comprising:
 determining a priority of access to the shared main memory for the first processing unit with a direct memory access (DMA) engine.   
     
     
         10 . The computing device method according to  claim 6 , comprising:
 determining a burst length of access to the shared main memory for the first processing unit with a direct memory access (DMA) engine.   
     
     
         11 . The computing device method according to  claim 1 , wherein arbitrating access to the shared main memory comprises:
 operating a state machine with at least three states, a first idle state indicating that no devices are accessing the shared main memory, a second busy state indicating one device is accessing the shared main memory, and a third queue state indicating that the one device is accessing the shared main memory and at least one other device is waiting to access the shared main memory.   
     
     
         12 . The computing device method according to  claim 1 , comprising:
 preventing the decoder/encoder from receiving consecutive accesses to the shared main memory when the first processing unit is waiting to access the shared main memory.   
     
     
         13 . The computing device method according to  claim 1 , comprising:
 preventing the first processing unit from receiving consecutive accesses to the shared main memory when the decoder/encoder is waiting to access the shared main memory.   
     
     
         14 . The computing device method according to  claim 1 , comprising:
 raising priority of the first processing unit to access the shared main memory when the first processing unit is waiting to access the shared main memory.   
     
     
         15 . The computing device method according to  claim 14  wherein raising priority of the first processing unit to access the shared main memory is based on a length of time a first main memory request is in a queue. 
     
     
         16 . The computing device method according to  claim 1 , comprising:
 raising priority of the decoder/encoder to access the shared main memory when the decoder/encoder is waiting to access the shared main memory.   
     
     
         17 . The computing device method according to  claim 16  wherein raising priority of the decoder/encoder to access the shared main memory is based on a length of time a second main memory request is in a queue. 
     
     
         18 . The computing device method according to  claim 1 , comprising:
 preempting first processing unit access to the shared main memory when the decoder/encoder is waiting to access the shared main memory.   
     
     
         19 . The computing device method according to  claim 1 , comprising:
 preempting decoder/encoder access to the shared main memory when the first processing unit is waiting to access the shared main memory.   
     
     
         20 . The computing device method according to  claim 1 , wherein executing the software instructions comprises:
 executing at least one two-dimensional (2D) graphics accelerator software instructions or at least one three-dimensional (3D) graphics accelerator software instructions.