High-Voltage Tolerant Biasing Arrangement Using Low-Voltage Devices

Abstract

A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.

1 - 21 . (canceled) 
     
     
         22 . A method for generating a reference signal that is substantially constant over a prescribed range of process, supply voltage and temperature conditions, the method comprising steps of:
 providing a high-voltage tolerant reference circuit that utilizes low voltage transistors, the reference circuit being adapted to receive first and second bias signals and being operative to generate the reference signal, a magnitude of the reference signal being controlled as a function of the first and second bias signals;   generating the first and second bias signals such that when the magnitude of the reference signal is within prescribed limits of a quiescent value of the reference signal, a magnitude of a current in the reference circuit is substantially constant and below a first value, and when the magnitude of the reference signal is outside of the prescribed limits, the magnitude of the current in the reference circuit increases nonlinearly above the first value to thereby restore the magnitude of the reference signal to within the prescribed limits of its quiescent value.   
     
     
         23 . The method of  claim 22 , further comprising:
 connecting a first source/drain of a first NMOS transistor in the reference circuit with a first voltage supply, a gate of the first NMOS transistor receiving the first bias signal;   connecting a first source/drain of a first PMOS transistor in the reference circuit with a second voltage supply that is lower in magnitude than the first voltage supply, a gate of the first PMOS transistor receiving the second bias signal; and   connecting a second source/drain of the first PMOS transistor with a second source/drain of the first NMOS transistor at an output of the reference circuit.   
     
     
         24 . The method of  claim 23 , further comprising providing a bias circuit for generating the first and second bias signals. 
     
     
         25 . The method of  claim 24 , further comprising configuring the bias circuit to include a first cascode current mirror operative to generate the first bias signal and a second cascode current mirror operative to generate the second bias signal. 
     
     
         26 . The method of  claim 25 , further comprising:
 providing second, third, fourth, and fifth NMOS transistors in the first cascode current mirror, a first source/drain of the second and third NMOS transistors being adapted for connection with the second voltage supply, a gate and a second source/drain of the second NMOS transistor being connected with a gate of the third NMOS transistor, a first source/drain of the fourth NMOS transistor being connected with the second source/drain of the second NMOS transistor, a gate and a second source/drain of the fourth NMOS transistor being connected with a gate of the fifth NMOS transistor, a first source/drain of the fifth NMOS transistor being connected with a second source/drain of the third NMOS transistor; and   providing first and second resistors in the first cascode current mirror, a first terminal of the first resistor being connected with the second source/drain of the fourth NMOS transistor, a second terminal of the first resistor being adapted for connection with the first voltage supply, a first terminal of the second resistor being connected with a second source/drain of the fifth NMOS transistor and forming an output of the first cascode current mirror for generating the first bias signal, and a second terminal of the second resistor being adapted for connection with the first voltage supply.   
     
     
         27 . The method of  claim 26 , further comprising controlling a magnitude of the first bias signal as a function of a ratio of the first and second resistors. 
     
     
         28 . The method of  claim 25 , further comprising:
 providing second, third, fourth, and fifth PMOS transistors in the second cascode current mirror, a first source/drain of the second and third PMOS transistors being adapted for connection with the first voltage supply, a gate and a second source/drain of the second PMOS transistor being connected with a gate of the third PMOS transistor, a first source/drain of the fourth PMOS transistor being connected with the second source/drain of the second PMOS transistor, a gate and a second source/drain of the fourth PMOS transistor being connected with a gate of the fifth PMOS transistor, a first source/drain of the fifth PMOS transistor being connected with a second source/drain of the third PMOS transistor; and   providing first and second resistors in the second cascode current mirror, a first terminal of the first resistor being connected with the second source/drain of the fourth PMOS transistor, a second terminal of the first resistor being adapted for connection with the second voltage supply, a first terminal of the second resistor being connected with a second source/drain of the fifth PMOS transistor and forming an output of the second cascode current mirror for generating the second bias signal, and a second terminal of the second resistor being adapted for connection with the second voltage supply.   
     
     
         29 . The method of  claim 23 , further comprising controlling a magnitude of the reference signal to be about half a difference between the first and second voltage supplies over a prescribed range of process, supply voltage and temperature conditions to which the reference circuit is subjected. 
     
     
         30 . The method of  claim 23 , further comprising controlling a magnitude of the first bias signal to be about an NMOS threshold voltage above a mid-point between the first and second voltage supplies over a prescribed range of process, supply voltage and temperature conditions to which the reference circuit is subjected. 
     
     
         31 . The method of  claim 23 , further comprising controlling a magnitude of the second bias signal to be about a PMOS threshold voltage below a mid-point between the first and second voltage supplies over a prescribed range of process, supply voltage and temperature conditions to which the reference circuit is subjected. 
     
     
         32 . The method of  claim 23 , wherein each of the first NMOS and first PMOS transistors are low voltage transistors. 
     
     
         33 . The method of  claim 22 , further comprising controlling the reference signal as a function of the respective magnitudes of each of the first and second bias signals such that the magnitude of the current in the reference circuit increases nonlinearly when the reference signal changes from its quiescent value.