Data control circuit

Abstract

A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.

What is claimed is: 
     
         1 . A data control circuit comprising:
 an output stage circuit outputting a data signal;   a switch circuit, an input terminal of the switch circuit being coupled to an output terminal of the output stage circuit, an output terminal of the switch circuit being coupled to a post-stage circuit, wherein the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit according to a control of a control signal; and   an impedance module configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit, wherein the impedance module reduces noise flowing from the switch circuit to the output stage circuit.   
     
     
         2 . The data control circuit as recited in  claim 1 , wherein the output stage circuit comprises:
 a first inverter circuit, an input terminal of the first inverter circuit being coupled to an input terminal of the output stage circuit, an output terminal of the first inverter circuit being coupled to the output terminal of the output stage circuit.   
     
     
         3 . The data control circuit as recited in  claim 2 , wherein the first inverter circuit comprises:
 a first n-type transistor, a source terminal of the first n-type transistor being coupled to a ground voltage, a drain terminal of the first n-type transistor being coupled to the output terminal of the output stage circuit, a gate terminal of the first n-type transistor being coupled to the input terminal of the output stage circuit; and   a first p-type transistor, a gate terminal of the first p-type transistor being coupled to the gate terminal of the first n-type transistor, a drain terminal of the first p-type transistor being coupled to the drain terminal of the first n-type transistor, a source terminal of the first p-type transistor being coupled to a system voltage.   
     
     
         4 . The data control circuit as recited in  claim 3 , wherein the impedance module is coupled between the source terminal of the first n-type transistor and the ground voltage. 
     
     
         5 . The data control circuit as recited in  claim 3 , wherein the impedance module is coupled between the source terminal of the first p-type transistor and the system voltage. 
     
     
         6 . The data control circuit as recited in  claim 3 , wherein the impedance module is coupled between the drain terminal of the first n-type transistor and the output terminal of the output stage circuit. 
     
     
         7 . The data control circuit as recited in  claim 3 , wherein the impedance module is coupled between the drain terminal of the first p-type transistor and the output terminal of the output stage circuit. 
     
     
         8 . The data control circuit as recited in  claim 2 , wherein the output stage circuit further comprises:
 a second inverter circuit, an input terminal of the second inverter circuit being coupled to the output terminal of the first inverter circuit, an output terminal of the second inverter circuit being coupled to the input terminal of the first inverter circuit.   
     
     
         9 . The data control circuit as recited in  claim 8 , wherein the second inverter circuit comprises:
 a second p-type transistor, a source terminal of the second p-type transistor being coupled to a system voltage, a gate terminal of the second p-type transistor being coupled to the input terminal of the second inverter circuit, a drain terminal of the second p-type transistor being coupled to the output terminal of the second inverter circuit; and   a second n-type transistor, a drain terminal of the second n-type transistor being coupled to the drain terminal of the second p-type transistor, a source terminal of the second n-type transistor being coupled to a ground voltage, a gate terminal of the second n-type transistor being coupled to the input terminal of the second inverter circuit.   
     
     
         10 . The data control circuit as recited in  claim 8 , wherein the second inverter circuit comprises:
 a second p-type transistor, a source terminal of the second p-type transistor being coupled to a system voltage, a gate terminal of the second p-type transistor being coupled to the input terminal of the second inverter circuit;   a third p-type transistor, a source terminal of the third p-type transistor being coupled to a drain terminal of the second p-type transistor, a drain terminal of the third p-type transistor being coupled to the output terminal of the second inverter circuit, a gate terminal of the third p-type transistor being controlled by a clock signal;   a second n-type transistor, a drain terminal of the second n-type transistor being coupled to the drain terminal of the third p-type transistor, a gate terminal of the second n-type transistor being controlled by an inverting signal of the clock signal; and   a third n-type transistor, a drain terminal of the third n-type transistor being coupled to a source terminal of the second n-type transistor, a source terminal of the third n-type transistor being coupled to a ground voltage, a gate terminal of the third n-type transistor being coupled to the input terminal of the second inverter circuit.   
     
     
         11 . The data control circuit as recited in  claim 1 , wherein the switch circuit comprises:
 a second n-type transistor, a source terminal of the second n-type transistor being coupled to the output terminal of the switch circuit, a drain terminal of the second n-type transistor being coupled to the input terminal of the switch circuit, a gate terminal of the second n-type transistor being controlled by the control signal.   
     
     
         12 . The data control circuit as recited in  claim 11 , wherein the impedance module is coupled between the drain terminal of the second n-type transistor and the input terminal of the switch circuit. 
     
     
         13 . The data control circuit as recited in  claim 11 , wherein the switch circuit further comprises:
 a second p-type transistor, a source terminal of the second p-type transistor being coupled to the input terminal of the switch circuit, a drain terminal of the second p-type transistor being coupled to the output terminal of the switch circuit, a gate terminal of the second p-type transistor being controlled by an inverting signal of the control signal.   
     
     
         14 . The data control circuit as recited in  claim 1 , wherein the switch circuit comprises:
 a second p-type transistor, a source terminal of the second p-type transistor being coupled to the input terminal of the switch circuit, a drain terminal of the second p-type transistor being coupled to the output terminal of the switch circuit, a gate terminal of the second p-type transistor being controlled by the control signal.   
     
     
         15 . The data control circuit as recited in  claim 14 , wherein the impedance module is coupled between the source terminal of the second p-type transistor and the input terminal of the switch circuit. 
     
     
         16 . The data control circuit as recited in  claim 1 , wherein the impedance module is coupled between the output terminal of the output stage circuit and the input terminal of the switch circuit. 
     
     
         17 . The data control circuit as recited in  claim 1 , wherein the impedance module is at least one resistor, an n-type transistor, or a p-type transistor.